Image fusion is a data fusion technology which keeps images as main research contents. It refers to the techniques that integrate multi-images of the same scene from multiple image sensor data or ...integrate multi images of the same scene at different times from one image sensor. In this paper Wavelet based Image fusion algorithm is employed and implemented on a Field-Programmable-Gate Array-based hardware system using a Xilinx Platform Studio EDK 10.1 FPGA Spartan 3E is implemented. The FPGA technologies offer basic digital blocks with flexible interconnections to achieve high speed digital hardware realization. The FPGA consists of a system of logic blocks, such as Look up Tables, gates, or flip-flops and some amount of memory. Finally, the proposed algorithm in this project was applied to experiments of multi-focus image fusion and complementary image fusion. The algorithm will be transferred from computer to FPGA board using JTAG cable. The result will be transferred back to system to analyze hardware resource taken by FPGA using Visual Basic.
Pipelined and folded energy - Efficientfft processors Chand, K. Sai; Kumar, A. V. Susmith; Avinash, Y. ...
2016 International Conference on Inventive Computation Technologies (ICICT),
2016-Aug., Letnik:
1
Conference Proceeding
This paper describes the design of a low area, power efficient and high performance Fast Fourier Transform (FFT) processor using an energy efficient adder architecture and a mod-ified booth ...multiplier architecture in place of the ordinary CMOS logic adder circuit and multiplier circuit, respectively. Variable supply voltage (VSV) scaling was implemented in the processor which is an efficient way to reduce energy consumption by lowering the operating voltage and determining the non-critical path of the processor simultaneously. Low power was obtained using hybrid robust adder which uses pass transistor logic and constant voltage scaling. High performance was achieved by using pipelining and parallel processing whereas low area was attained by using the folding architecture. 90nm technology architecture was designed and used to verify the functionality of the proposed system showing the power consumption and computational time in Cadence.
This paper propounds the design of a wearable wideband antenna loaded with a DRA (Dielectric Resonator Antenna) to achieve greater bandwidth characteristics. The wearable wideband antenna is designed ...on a jean substrate of thickness 0.6mm which has a ε r (dielectric constant)value of 1.73. The proposed antenna is made to operate in the wideband range of 2.7GHz to 15GHz. The radiator is modified to achieve more efficient return loss. The jean substrate chosen is ideal for textile and on body wearable applications. The DRA is a ceramic alumina material of cylindrical shape loaded on to the antenna to reduce the specific absorption rate and the radiation pattern maintains a stable omnidirectional characteristics.
Traditional static traffic assignment models no longer meet the strategic planning needs of most major metropolitan areas, especially in regard to evaluating major infrastructure projects. One ...promising possibility is dynamic traffic assignment (DTA), which has been receiving greater attention in the research community for the last ten years. This work describes the ongoing experience of building the first large-scale DTA model in Australia. We divide our experiences into categories regarding data, implementation, and visualization, and we discuss the challenges faced as well as our methods for overcoming those challenges. Finally, we discuss initial model results and the calibration process. In the future, the DTA model described here could aid in evaluating important policy decisions and infrastructural development in the context of the macro/meso-scale network operation. This project serves as a proof of concept for the Australia region and may provide valuable insight to other practitioners interested in emerging areas of transport planning and traffic modeling.
BIST TPG (built in self test) for low power dissipation and high fault coverage presents a low hardware overhead test pattern generator (TPG) for scan-based built-in self-test (BIST) that can reduce ...switching activity in circuits under test (CUTs) during BIST and also achieve very high fault coverage with reasonable lengths of test sequences. The proposed BIST TPG decreases transitions that occur at scan inputs during scan shift operations and hence reduces switching activity in the CUT. The BIST TPG comprises of two TPG's, LT-RTPG and 3-weight WRBIST. Test patterns generated by the LT-RTPG detect easy-to-detect faults and test patterns generated by the 3-weight WRBIST detect faults that remain undetected after LT-RTPG patterns are applied. The BIST TPG does not require modification of mission logics, which can lead to performance degradation. Recently, techniques to reduce switching activity during BIST have been proposed. A straightforward solution is to reduce the speed of the test clock during scan shift operations. However, since most test application time of scan-based BIST is spent for scan shift operations, this will increase test application time by about a factor of if scan flip-flops are clocked at speed during scan shift operations. Larger reduction in switching activity is achieved in large circuits. Experimental results also show that the BIST-TPG can be implemented with low area overhead. Larger reduction in switching activity is achieved in large circuits. Experimental results also show that the BIST-TPG can be implemented with low area overhead.
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