Importance of Error Correcting Codes (ECCs) is increasing rapidly for protecting memories from localized errors. These localized errors in memories are mainly due to radiation induced soft errors ...which corrupt data stored in a single cell or multiple cells of a memory. Initially, Single Error Correction (SEC) and Single Error Correction-Double Error Detection (SEC-DED) codes have been widely introduced to protect memories against soft errors. But with the incessant down scaling of technology node, the chances of multiple errors in memory cells are increasing day by day. The most common errors in multiple memory cells are the single error and double-adjacent errors. These errors are corrected by employing Single Error Correction- Double Adjacent Error Correction (SEC-DAEC) codes. But the major challenges in designing SEC-DAEC codes are higher decoding overheads and higher miscorrection rate. In this paper, the
H
-matrices for a new class of SEC-DAEC codes have been proposed to reduce the decoding overheads. The proposed codecs have been designed and synthesized in ASIC platform with suitable word lengths for memories. Both the theoretical and synthesis results for proposed codecs have been compared with recently published related works. These comparisons show that proposed (24, 16) codec requires a maximum of 1.38 times and 1.74 times lower area and delay respectively compared to other related codecs of same word length. Also the proposed 64-bit codec consumes a highest of 2.75 times lesser power with respect to existing 64-bit codecs. Thus the proposed codecs can be employed in memories for correcting single and double-adjacent errors with improved area, delay and power requirements.
Internet of Things (IoT) technology adds new direction to the significant monitoring of soil, plants, and agriculture fields in smart agriculture. In this system, IoT-based solutions are employed to ...enhance the agricultural outcomes and resolve the different problems. Here, an IoT-based device is proposed namely “SmartTech-Agri.” This device is designed to supervise the different parameters: soil moisture, air temperature, air humidity, smoke detection, and animal motion detection in the agricultural field. Our proposed device uses a PIR motion sensor to detect movement of intruders, smoke sensor to detect smoke, soil moisture sensor to evaluate moisture percentage, and temperature–humidity sensor to measure environmental temperature in the agriculture field. The proposed design consists of three main major portions: (a) an Arduino-based IoT gadget, (b) a Smartphone application, and (c) a Web server application. The SmartTech-Agri can evaluate different parameters and instantly communicate vital associated information via web-based technologies. The proposed design has been compared with existing recent related works. The accuracy of our device varies from − 2.82 to + 3.85% for humidity and − 2.66 to + 3.14% in case of temperature. This low-cost technology can be utilized for farming production and management in a convenient and effective manner. This approach will lower the overall labor costs and cut down on water waste.
This paper proposed the design and development of reversible cost-efficient innovative quantum dual-full adder and subtractor or QD-FAS circuit using quantum gate. The proposed circuit can be used as ...full adder and full subtractor simultaneously, which is designed using double Peres gate or DPG and Feynman gate or FG. The quantum cost, garbage output and constant input of the QD-FAS is 8, 1 and 1. Which is better w.r.t previously reported work. The QD-FAS circuit, as proposed, includes shared sum and difference terminals, as well as a carry-out and a borrow output terminal. Notably, this innovation showcases a remarkable 27.27% reduction in quantum cost. The improvement in garbage output is even more striking, showing a 50% enhancement. When assessing the overall advancement in quantum cost, it falls within the range of 27.27% to 66.66%. To confirm the viability of this design, extensive testing is carried out using the IBM Qiskit simulator. This design holds significant importance in a variety of applications, including quantum computing, cryptography, and the realm of reversible Arithmetic Logic Units (ALU).
Reliability of Static Random Access Memories (SRAMs) is immensely affected by radiation induced soft errors. Multiple Cell Upsets (MCUs) are caused by these soft errors and this lead to data ...corruption in several SRAM cells. Error Correcting Codes are normally exploited to alleviate the effect of MCUs. Single Error Correction–Double Error Detection (SEC–DED) codes are not the appropriate preference against MCUs rather these codes are suitable for protecting SRAM cells against Single Cell Upset. Single Error Correction–Double Error Detection–Double Adjacent Error Correction (SEC–DED–DAEC) codes are more suitable due to increasing trends of single and double-adjacent errors in SRAM cells. In this paper, a new SEC–DED–DAEC code has been proposed which is proficient of correcting single and double-adjacent errors in SRAMs. Our newly proposed code has been termed as Single and Double-adjacent Error Correcting Code (SDECC). Proposed codecs have been designed by employing new parity check matrices for different word lengths which are frequently applied in memory. The mis-correction probability of proposed SDECC codes are up to 88.24% and 80.67% lesser for 2-random and 3-random bit errors respectively with respect to related existing designs. Proposed codecs have been replicated and synthesized in ASIC environment. It is observed that area and power consumption of the proposed codecs are reduced up to 8.93% and 21.47% compared to the recently published results respectively.
This comment points out the mistakes of one figure, one flowchart, and six tables in reference
1
.
Here we have provided the corrected version of figure, flowchart, and tables.
Frequently, soft errors occur due to striking of radioactive particles in memory cells which reduce the reliability of memory systems. Generally, single error correction-double error detection ...(SEC-DED) codes are employed to detect and correct the soft errors in semiconductor memory systems. In this paper, a new optimization algorithm is proposed based on common sub-expression elimination method. By employing this proposed optimization algorithm, more simplified expressions for encoder and decoder are obtained from parity check matrix (
H
-matrix). Proposed optimization technique has been used to implement seven different SEC-DED codecs with message length of 8 bits, 16 bits, 32 bits, 64 bits, 128 bits, 256 bits and 512 bits. Compact design requires at most 21.66% lesser number of two-input XOR gates compared to related SEC-DED codes. All codec architectures are simulated and synthesized using both FPGA and ASIC platforms. Area and power consumption of proposed designs are reduced compared to the existing design without affecting its speed. Proposed designs are beneficial in computer memory systems due to its compactness and lower power consumption.
Memory contents are usually corrupted due to soft errors caused by external radiation and hence the reliability of memory systems is reduced. In order to enhance the reliability of memory systems, ...error correcting codes (ECC) are widely used to detect and correct errors. Single bit error correcting with double bits errors detecting codes are generally used in memory systems. But in case of multiple cell errors, these codes are unable to detect and correct errors. Recently, single byte error correcting Reed Solomon (SEC-RS) codes are used to detect and correct single byte error in memory systems. In this paper, a new single byte error correcting (SEC) code is proposed based on the concept of cellular automata (termed as CASEC). The main aim of this work is to reduce the area and power of SEC encoder and decoder circuit without affecting delay. In this paper, CASEC(10,8,8), CASEC(18,16,8), 2xCASEC(10,8,4) and 2xCASEC(19,6,4) codecs are designed and implemented. CASEC(18,16,8) codec has 67.79 percent lesser hardware complexity compared to existing design. Proposed codecs are simulated and synthesized for both FPGA and ASIC platforms. It is found that speed of the proposed design is almost equal to the existing design but requires lesser area and power. Area-delay product (ADP) of proposed CASEC(10,8,8), CASEC(18,16,8), 2xCASEC(10,8,4) codecs are better compared to the existing designs.
Multiple cell upsets (MCUs) caused by radiation is an important issue related to the reliability of embedded static random access memories (SRAMs). Multiple random and adjacent error correcting codes ...have been extensively employed for several years to protect stored data in SRAMs against MCUs. A compact and fast error correcting codec is desirable in most of these applications. In this study, simplified expressions for error location detection (ELD) block for single error correction-double error detection-double adjacent error correction (SEC-DED-DAEC) and single error correction-double error detection-triple adjacent error correction (SEC-DED-TAEC) decoders have been obtained by employing Karnaugh map. The conventional SEC-DED-DAEC and SEC-DED-TAEC decoders have been designed and implemented in both field-programmable gate array and ASIC platforms by considering these simplified ELD expressions. In FPGA platform, the proposed design for SEC-DED-DAEC and SEC-DED-TAEC decoders require 1.37–28.40% improvement in area and maximum 14.74% improvement in delay compared to existing designs. Whereas ASIC-based designs provide 2.20–26.81% reduction in area and 0.30–28.96% reduction in delay compared to existing related works. So the proposed design can be considered as an efficient alternative of traditional adjacent error correcting decoders in resource constraint applications.
This paper comments on the some mistakes which have been observed in Tripathi et al. (2023) 1. We have specifically pointed out the following mistakes of Tripathi et al. (2023) 1.
i) Presented (41, ...32) SEC-DAEC-TAEC H-matrix in Fig. 3 of Tripathi et al. (2023) 1.
ii) Presented error detection and correction coverage in Table 6 of Tripathi et al. (2023) 1.
The corrected versions of the above mentioned mistakes have been presented in this paper. Also the FPGA-based synthesis result of corrected encoder and decoder circuits based on the corrected (41, 32) H-matrix have been presented here.
FPGA based area efficient RS(23, 17) codec Samanta, Jagannath; Bhaumik, Jaydeb; Barman, Soma
Microsystem technologies : sensors, actuators, systems integration,
03/2017, Letnik:
23, Številka:
3
Journal Article
Recenzirano
Generally in digital communication systems and storage mediums, Reed–Solomon (RS) codes are employed to detect and correct errors. RS code is a promising code for Ultra Wide Band (UWB) which is ...ideally suitable for wireless application. Design of compact, high-speed and low-power RS(23, 17) code is challenging for today’s wireless communication systems. Here, an optimization algorithm is introduced which is very simple and it is employed to reduce the number of XOR gates required to design constant Galois Field (GF) multipliers. In this paper, a compact RS(23, 17) encoder and decoder circuit is designed and implemented for Ultra Wide Band(UWB) application. The number of two input XOR gates is reduced by 29.27 (20.00) and 56.10 (66.15) % respectively for local and global optimization compared to unoptimized RS encoder (syndrome block) without increasing its delay. The proposed algorithm is also employed to design the RS(204, 188) and RS(255, 223) encoder. All designs are simulated and synthesized for Vertex4 FPGA platform. Proposed algorithm is also used for the design of Chien Search and Forney blocks. Implemented RS(23, 17) codec requires lesser number of slices and LUTs over the unoptimized RS codec. The synthesis results reflect that the proposed design is suitable for resource constraint applications.
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