Strained silicon on insulator wafers are today envisioned as a natural and powerful enhancement to standard SOI wafers and/or bulk-like strained Si layers. This paper is intended to demonstrate ...through miscellaneous structural results how a layer transfer technique such as the Smart Cut
TM technology can be used to obtain good quality tensile-strained silicon on insulator wafers. Such a technique uses preferentially hydrogen implantation to peel-off the very top part of an epitaxial stack and transfer it onto another silicon substrate. The formation of an insulator, prior to the bonding onto a new silicon substrate enables the formation of a “semiconductor on insulator” structure. Two approaches based on the Smart Cut technique are considered in this paper. The first one relies on the formation by layer transfer of a relaxed SiGe on insulator (“SGOI”) substrate on which a tensile-strained Si layer is then grown. The second one is based on the transfer of a SiGe relaxed buffer/Si cap stack. A SiGe-free tensile-silicon on insulator (sSOI) substrate is then obtained after the selective etching of the top SiGe layer. The epitaxial layers studied in this article are of two kinds: (i) the thick, nearly fully relaxed SiGe layers (with or without tensile-strained Si layers on top depending on the final structure targeted: SGOI or sSOI) used as the donor wafers in layer transfer operations, and (ii) the thin, relaxed SiGe layers and the thin, tensile-strained Si epitaxial films grown on SGOI substrates. In-depth physical characterizations of these epitaxial layers are used to evaluate the quality of the transferred layers in terms of thickness uniformity, Ge content, strain control, dislocation densities etc… Detailed experiments are also used to demonstrate that these final substrates are compatible with future CMOS applications. The sSOI approach is particularly challenging in this respect as the strain needs to be maintained during many technological operations such as layer transfer, selective removal of the SiGe, high temperature thermal treatments etc. First results showing how the strain is changing during such operations are presented.
Charging and discharging phenomena from Si nanocrystals have been studied by c-v characteristics on p-type MOS (P-MOS) capacitors with embedded self-assembled Si quantum dots. The dots have a ...floating gate behavior as shown by the hysteresis on C-V curves. The Si-dots are charged or discharged by direct tunneling of carriers through a 3 nm thick oxide. The nanocrystals could be charged by electrons or holes, depending on the charging bias conditions. The discharge is studied by constant bias method and shows a logarithmic variation with time. Retention times higher than several hours are observed. A simple model is developed in order to evaluate the electric field within the tunneling oxide layer. Then, complete simulations are done for the different discharge paths. The barrier heights are extracted from the discharge data and possible confinement effects are discussed. The results confirm the high potentiality of Si nanocrystal-floating gates for memory applications. 16 refs.
Charging and discharging phenomena from silicon nanocrystals have been studied by means of capacitance–voltage characteristics on P-type metal-oxide-semiconductor (P-MOS) capacitors with embedded ...self-assembled silicon quantum dots. The dots have a floating gate behavior as shown by the hysteresis onC –V curves. The Si-dots are charged or discharged by direct tunneling of carriers through a 3 nm thick oxide. The nanocrystals could be charged by electrons or holes, depending on the charging bias conditions. The discharge is studied by constant bias method and shows a logarithmic variation with time. Retention times higher than several hours are observed. A simple model is developed in order to evaluate the electric field within the tunneling oxide layer. Then, complete simulations are done for the different discharge paths. The barrier heights are extracted from the discharge data and possible confinement effects are discussed. The results confirm the high potentiality of silicon nanocrystal-floating gates for memory applications.
In this paper, we have correlated electrical measurements of thin HfO
2 layers deposited on SiO
2 by atomic layer deposition with angle-resolved X-ray photoelectron spectroscopy experiments. Results ...show that the HfO
2/Si interface layer (IL) is made of a SiO
x
layer underneath a Si-rich Hf-silicate layer. The increasing of the IL thickness, during annealing, was essentially due to the silicon oxidation by –OH groups remaining in the HfO
2 layer after deposition. Using shorter water pulse time, we were able to limit the SiO
x
growth during deposition. We have also observed, after annealing at 800 °C under nitrogen, a decreasing of the interfacial layer electrical thickness as well as an improvement of the equivalent oxide thickness of the stack.
For the first time, memory devices with optimized high density (2E12#/cm/sup 2/) LPCVD Si nanocrystals have been reproducibly achieved and studied on an extensive statistical basis (from single cell ...up to 1 Mb test-array) under different programming conditions. An original experimental and theoretical analysis of the threshold voltage shift distribution shows that Si nanocrystals have serious potential to push the scaling of NOR and NAND flash at least to the 35 nm and 65 nm nodes, respectively.
We report on 40 nm nMOS transistors with HfO/sub 2/ dielectric and polySi gate integrated into a damascene structure. We fabricated HfO/sub 2/ ALD layers with EOT down to 15 /spl Aring/, exhibiting ...leakage current more than two decades lower than SiO/sub 2/. Small mobility degradation on 2 nm EOT nMOSFETs was observed leading to the best performances (Ion= 680 /spl mu/A//spl mu/m @ Ioff=230 nA//spl mu/m) ever obtained with HfO/sub 2/ and polySi electrodes.
The anatomical and physiological relation between temporal muscle and temporomandibular joint are well-knowed. The versatility of the temporo muscle-fascia flap must be stressed. The posterior ...temporal flap is a simply, reliable procedure, with low morbidity. This technique is probably the procedure of choice in discal replacement and in interposition arthroplasty for ankylosis.
