Two-dimensional (2D) materials, such as graphene (Gr), transition metal dichalcogenides (TMDs) and hexagonal boron nitride (h-BN), offer interesting opportunities for the implementation of vertical ...transistors for digital and high-frequency electronics. This paper reviews recent developments in this field, presenting the main vertical device architectures based on 2D/2D or 2D/3D material heterostructures proposed so far. For each of them, the working principles and the targeted application field are discussed. In particular, tunneling field effect transistors (TFETs) for beyond-CMOS low power digital applications are presented, including resonant tunneling transistors based on Gr/h-BN/Gr stacks and band-to-band tunneling transistors based on heterojunctions of different semiconductor layered materials. Furthermore, recent experimental work on the implementation of the hot electron transistor (HET) with the Gr base is reviewed, due to the predicted potential of this device for ultra-high frequency operation in the THz range. Finally, the material sciences issues and the open challenges for the realization of 2D material-based vertical transistors at a large scale for future industrial applications are discussed.
A nanoscale investigation on the capacitive behavior of graphene deposited on a SiO2/n+ Si substrate (with SiO2 thickness of 300 or 100 nm) was carried out by scanning capacitance spectroscopy (SCS). ...A bias V g composed by an AC signal and a slow DC voltage ramp was applied to the macroscopic n+ Si backgate of the graphene/SiO2/Si capacitor, while a nanoscale contact was obtained on graphene by the atomic force microscope tip. This study revealed that the capacitor effective area (A eff) responding to the AC bias is much smaller than the geometrical area of the graphene sheet. This area is related to the length scale on which the externally applied potential decays in graphene, that is, the screening length of the graphene 2DEG. The nonstationary charges (electrons/holes) induced by the AC potential spread within this area around the contact. A eff increases linearly with the bias and in a symmetric way for bias inversion. For each bias V g, the value of A eff is related to the minimum area necessary to accommodate the not stationary charges, according to the graphene density of states (DOS) at V g. Interestingly, by decreasing the SiO2 thickness from 300 to 100 nm, the slope of the A eff versus bias curve strongly increases (by a factor of ∼50). The local quantum capacitance C q in the contacted graphene region was calculated starting from the screening length, and the distribution of the values of C q for different tip positions was obtained. Finally the lateral variations of the DOS in graphene was determined.
This paper presents an analysis of junction leakage in heavily doped p+/n germanium junctions, targeted for short-channel transistor fabrication. There exists an optimal p+/n junction condition, with ...a doping concentration of 1 times 10 17 -5 times 10 17 cm -3 , where the area-leakage-current density is minimal. Use of a halo-implant condition optimized for our 125-nm gate-length pMOS devices shows less than one decade higher area leakage than the optimal p+/n junction. For even higher doping levels, the leakage density increases strongly. Therefore, careful optimization of p+/n junctions is needed for decananometer germanium transistors. The junction leakage shows good agreement with electrical simulations, although for some implant conditions, more adequate implant models are required. Finally, it is shown that the area-junction static-power consumption for the best junctions remains below the power-density specifications for high-performance applications.
Graphene deposited on silicon dioxide (DG-SiO2) and high-κ dielectric strontium titanate (DG-STO) are investigated for electrostatic properties by local capacitance measurements carried out with ...Scanning Capacitance Spectroscopy (SCS). The quantum capacitance associated with 2DEG in graphene showed significant increase for DG-STO as a function of Fermi level (EF) as compared to that for DG-SiO2. The quantum capacitance, being a fundamental property of graphene 2DEG, is not expected to vary with substrate dielectric properties in the absence of any interaction. However, the observed increase in quantum capacitance in our case is predominantly due to the enhanced effectively biased area in DG-STO. We suggest that this effect is a consequence of better dielectric screening of commonly observed charged impurities, on graphene and/or at the graphene/substrate interface, by the use of high permittivity substrate.
► Local quantum capacitance is evaluated for graphene on strontium titanate (DG-STO). ► Results are compared with graphene on silicon dioxide (DG-SiO2). ► Higher quantum capacitance for DG-STO is due to higher effectively biased area. ► Better screening of charged impurities is based on high-κ dielectric.
Electrostatic properties, quantum capacitance (Cq) and local density of states (LDOS) are evaluated for graphene on 4H-SiC(0001) by measuring the local capacitance with Scanning Capacitance ...Spectroscopy (SCS). Two distinct samples were used for comparative study, viz., graphene exfoliated and deposited on 4H-SiC(0001)—DG, and graphene grown epitaxially on 4H-SiC(0001)—EG. We observed a distinctly lower screening length (rscr) and Cq while wider variations in the LDOS for EG. Such differences are attributed to the peculiar interface between EG/4H-SiC(0001), which is known to be more or less defective having the presence of positive charges.
► Local electrostatic properties are evaluated for graphene on 4H-SiC(0001). ► Lower screening length and Cq are observed for epitaxial graphene on 4H-SiC(0001). ► Such differences are attributed to the peculiar interface between EG/4H-SiC(0001). ► The results are compared with graphene deposited on 4H-SiC(0001).
The current transport across the graphene/4H-SiC interface has been investigated with nanometric lateral resolution by scanning current spectroscopy on both epitaxial graphene (EG) grown on (0001) ...4H-SiC and graphene exfoliated from highly oriented pyrolytic graphite deposited on the same substrate deposited graphene (DG). This study reveals that the Schottky barrier height (SBH) of EG/4H-SiC (0.36 +/- 0.1 eV) is similar to 0.49 eV lower than the SBH of DG/4H-SiC (0.85 +/- 0.06 eV). This result is discussed in terms of the Fermi-level pinning similar to 0.49 eV above the Dirac point in EG due to the presence of positively charged states at the interface between the Si face of 4H-SiC and the carbon-rich buffer layer, which is the precursor for EG formation.
The Paper describes the progress of electronics engineering education in India from early times to its present status as a large system, with some efforts devoted to quality enhancement and raising ...its standard. It also brings out the need for transforming this system to meet the challenges ahead for making India a knowledge society by the year 2020, and outlines some priorities in this connection.
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