Three-dimensional silicon integration Knickerbocker, J U; Andry, P S; Dang, B ...
IBM journal of research and development,
11/2008, Letnik:
52, Številka:
6
Journal Article
Recenzirano
Three-dimensional (3D) silicon integration of active devices with through-silicon vias (TSVs), thinned silicon, and silicon-to-silicon fine-pitch interconnections offers many product benefits. ...Advantages of these emerging 3D silicon integration technologies can include the following: power efficiency, performance enhancements, significant product miniaturization, cost reduction, and modular design for improved time to market. IBM research activities are aimed at providing design rules, structures, and processes that make 3D technology manufacturable for chips used in actual products on the basis of data from test-vehicle (i.e., prototype) design, fabrication, and characterization demonstrations. Three-dimensional integration can be applied to a wide range of interconnection densities (<10/cm^sup 2^ to 10^sup 8^/cm^sup 2^), requiring new architectures for product optimization and multiple options for fabrication. Demonstration test structures, which are designed, fabricated, and characterized, are used to generate experimental data, establish models and design guidelines, and help define processes for future product consideration. This paper 1) reviews technology integration from a historical perspective, 2) describes industry-wide progress in 3D technology with examples of TSV and silicon-silicon interconnection advancement over the last 10 years, 3) highlights 3D technology from IBM, including demonstration test vehicles used to develop ground rules, collect data, and evaluate reliability, and 4) provides examples of 3D emerging industry product applications that could create marketable systems. PUBLICATION ABSTRACT
As traditional CMOS scaling becomes progressively more difficult and less beneficial to overall system performance, three-dimensional silicon integration technologies have begun to receive ...considerable attention. An advanced packaging solution based on a thin silicon carrier has been developed to provide interconnection between integrated circuits (ICs) and other devices at densities far beyond those of current first-level packaging. The silicon carrier employs fine-pitch Cu damascene wiring, high-density solder interconnections, and through-silicon vias (TSVs). A key enabling technology element is the TSV, which may be naturally scaled to provide vertical interconnection in stacked ICs as well as silicon carriers. In this paper, we discuss the evolution in both TSV design and process flow that has led to TSV technology which produces vias with resistances on the order of 10-20 mΩ and yields on the order of 99.99% at wafer level in a research laboratory environment. Two generalized process approaches to forming TSVs are discussed, the "vias-first" and the "vias-last" methods, along with related advantages and potential drawbacks of each. Improvement to these process flows and structures is afforded by simple changes of via geometry from cylindrical to annular or from annular to multibar. While various TSV metallurgies are reviewed, tungsten is shown to be a nearly optimal choice. Results on via resistance, electrical yield, and current-carrying capacity are covered. The use of electrical modeling to predict structures with superior electrical and mechanical properties is also described. PUBLICATION ABSTRACT
System-on-Package (SOP) technology based on silicon carriers has the potential to provide modular design flexibility and high-performance integration of heterogeneous chip technologies and to support ...robust chip manufacturing with high-yield/low-cost chips for a wide range of two- and three-dimensional product applications. Key technology enablers include silicon through-vias, high-density wiring, high-I/O chip interconnection, and supporting test and assembly technologies. The silicon through-vias are a key feature permitting efficient area array signal, power, and ground interconnection through these thinned silicon packages. High-density wiring and high-density chip I/O interconnection can enable tight integration of heterogeneous chip technologies which approximate the performance of an integrated system-on-chip with a "virtual chip" using the silicon package for integration. Silicon carrier fabrication leverages existing manufacturing capability and mid-UV lithography to provide very dense package wiring following CMOS back-end-of-line design rules. Further, the thermal expansion of the silicon carrier package matches the chip, which helps maintain reliability even as the high-density chip microbump interconnections scale to smaller size. In addition to heterogeneous chip integration, SOP products may leverage the integration of passive components, active devices, and electrooptic structures to enhance system-level performance while also maintaining functional test capability and known good chips when needed. This paper describes the technical challenges and recent progress made in the development of silicon carrier technology for potential new applications. PUBLICATION ABSTRACT
Three-dimensional (3D) integration using through-silicon vias (TSVs) and low-volume lead-free solder interconnects allows the formation of high signal bandwidth, fine pitch, and short-distance ...interconnections in stacked dies. There are several approaches for 3D chip stacking including chip to chip, chip to wafer, and wafer to wafer. Chip-to-chip integration and chip-to-wafer integration offer the ability to stack known good dies, which can lead to higher yields without integrated redundancy. In the future, with structure and process optimization, wafer-to-wafer integration may provide an ultimate solution for the highest manufacturing throughput assuming a high yield and minimal loss of good dies and wafers. In the near term, chip-to-chip and chip-to-wafer integration may offer high yield, high flexibility, and high performance with added time-to-market advantages. In this work, results are reported for 3D integration after using a chip-to-wafer assembly process using 3D chip-stacking technology and fine-pitch interconnects with lead-free solder. Stacks of up to six dies were assembled and characterized using lead-free solder interconnections that were less than 6 µm in height. The average resistance of the TSV including the lead-free solder interconnect was as low as 21 mΩ. PUBLICATION ABSTRACT
Wafer-level 3D integration technology Koester, S. J.; Young, A. M.; Yu, R. R. ...
IBM journal of research and development,
11/2008, Letnik:
52, Številka:
6
Journal Article
Recenzirano
An overview of wafer-level three-dimensional (3D) integration technology is provided. The basic reasoning for pursuing 3D integration is presented, followed by a description of the possible process ...variations and integration schemes, as well as the process technology elements needed to implement 3D integrated circuits. Detailed descriptions of two wafer-level integration schemes implemented at IBM are given, and the challenges of bringing 3D integration into a production environment are discussed. PUBLICATION ABSTRACT
System-on-Chip (SOC) and System-on-Package (SOP) technologies each have advantages depending on application needs. As system architects and designers leverage ever-increasing CMOS technology ...densities, a range of two- and three-dimensional silicon integration technologies are emerging which will likely support next-generation high-volume electronic applications and may serve high-performance computing applications. This paper will discuss a few emerging technologies which offer opportunities for enhanced circuit performance, or reduced power as one example. Silicon-on-silicon integration may include three-dimensional (3-D) integration on-chip or may leverage chip stacking or chip integration on package. Common technology features include silicon through-vias, high-I/O interconnection and silicon-on-silicon either as 3-D integrated circuits, integrated chip stacks or silicon-on-silicon packages with passive function or high-bandwidth wiring. Silicon chips on silicon interposers with integrated function such as decoupling capacitors may provide a better module architecture compared to increased on-chip decoupling or off chip discrete capacitors mounted on package at the chip perimeter or underside of the package. Advanced silicon carrier package technology with fine pitch (50 mum) interconnection is described. This silicon carrier package contains silicon through-vias and offers >16times increase over standard chip I/O, a 20times to 100times increase in wiring density over traditional organic and ceramic packaging, and allows for integrated high-performance passives. Silicon carrier technology supports lithographic scaling and provides a basis for known good die (KGD) wafer testing. It may be considered for use in a number of applications including optoelectronic (OE) transceivers, silicon interposers with integrated decoupling capacitors, and mini-multi-chip modules (MMCMs) which integrate heterogeneous dies forming a single "virtual chip."
3D chip stacking with C4 technology Dang, B; Wright, S L; Andry, P S ...
IBM journal of research and development,
11/2008, Letnik:
52, Številka:
6
Journal Article
Recenzirano
Three-dimensional (3D) integration technology promises to continue enhancing integrated-circuit system performance with high bandwidth, low latency, low power, and a small form factor for a variety ...of applications. In this work, conventional C4 (controlled-collapse chip connection) technology is studied for robust interconnection between stacked thin chips. Various solder hierarchies to enable 3D chip stacking and packaging are investigated. Examples are presented to compare stacking schemes with sequential and parallel reflow. Chips as thin as 90 µm are stacked using conventional chip-placement and reflow processes, and the associated process challenges are investigated and discussed. Warpage of the thin chips is measured on various substrates. Rework of the chip stack has also been demonstrated through a temporary chip attachment operation, and the scalability of reworkable C4 is investigated. PUBLICATION ABSTRACT
Background
Critically ill patients with diabetes mellitus (DM) are at increased risk of in‐hospital complications and the optimal glycemic target for such patients remains unclear. A more liberal ...approach to glucose control has recently been suggested for patients with DM, but uncertainty remains regarding its impact on complications.
Methods
We aimed to test the hypothesis that complications would be more common with a liberal glycemic target in ICU patients with DM. Thus, we compared hospital‐acquired complications in the first 400 critically ill patients with DM included in a sequential before‐and‐after trial of liberal (glucose target: 10‐14 mmol/L) vs conventional (glucose target: 6‐10 mmol/L) glucose control.
Results
Of the 400 patients studied, 165 (82.5%) patients in the liberal and 177 (88.5%) in the conventional‐control group were coded for at least one hospital‐acquired complication (P = 0.09). When comparing clinically relevant complications diagnosed between ICU admission and hospital discharge, we found no difference in the odds for infectious (adjusted odds ratio aOR for liberal‐control: 1.15 95% CI: 0.68‐1.96, P = 0.60), cardiovascular (aOR 1.40 95% CI: 0.63‐3.12, P = 0.41) or neurological complications (aOR: 1.07 95% CI: 0.61‐1.86, P = 0.81), acute kidney injury (aOR 0.83 95% CI: 0.43‐1.58, P = 0.56) or hospital mortality (aOR: 1.09 95% CI: 0.59‐2.02, P = 0.77) between the liberal and the conventional‐control group.
Conclusion
In this prospective before‐and‐after study, liberal glucose control was not associated with an increased risk of hospital‐acquired infectious, cardiovascular, renal or neurological complications in critically ill patients with diabetes.
In this letter, the integration of CMOS-compatible thru-Si via (TSV) interconnects with deep-trench decoupling capacitors is demonstrated. Reliability test is performed with a 65-nm CMOS test chip on ...top of a 3-D Si interposer chip that contains 10 000 TSV interconnects. Multilayer stacking is also demonstrated, and capacitance density of 280 nF/mm 2 is achieved with two-layer Si interposer chip stacks.
PDF
