We present the first all-digital PLL and polar transmitter for mobile phones. They are part of a single-chip GSM/EDGE transceiver SoC fabricated in a 90 nm digital CMOS process. The circuits are ...architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrateable with a digital baseband and application processor. To achieve this, we exploit the new paradigm of a deep-submicron CMOS process environment by leveraging on the fast switching times of MOS transistors, the fine lithography and the precise device matching, while avoiding problems related to the limited voltage headroom. The transmitter architecture is fully digital and utilizes the wideband direct frequency modulation capability of the all-digital PLL. The amplitude modulation is realized digitally by regulating the number of active NMOS transistor switches in accordance with the instantaneous amplitude. The conventional RF frequency synthesizer architecture, based on a voltage-controlled oscillator and phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter. The transmitter performs GMSK modulation with less than 0.5/spl deg/ rms phase error, -165 dBc/Hz phase noise at 20 MHz offset, and 10 /spl mu/s settling time. The 8-PSK EDGE spectral mask is met with 1.2% EVM. The transmitter occupies 1.5 mm/sup 2/ and consumes 42 mA at 1.2 V supply while producing 6 dBm RF output power.
We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process. The transceiver is architectured from the ground up to be compatible with digital deep-submicron ...CMOS processes and be readily integrated with a digital baseband and application processor. The conventional RF frequency synthesizer architecture, based on the voltage-controlled oscillator and the phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter, respectively. The transmitter architecture takes advantage of the wideband frequency modulation capability of the all-digital phase-locked loop with built-in automatic compensation to ensure modulation accuracy. The receiver employs a discrete-time architecture in which the RF signal is directly sampled and processed using analog and digital signal processing techniques. The complete chip also integrates power management functions and a digital baseband processor. Application of the presented ideas has resulted in significant area and power savings while producing structures that are amenable to migration to more advanced deep-submicron processes, as they become available. The entire IC occupies 10 mm/sup 2/ and consumes 28 mA during transmit and 41 mA during receive at 1.5-V supply.
Analytic view on coupled single-electron lines Pomorski, Krzysztof; Giounanlis, Panagiotis; Blokhina, Elena ...
Semiconductor science and technology,
12/2019, Letnik:
34, Številka:
12
Journal Article
Recenzirano
Odprti dostop
The fundamental properties of two electrostatically interacting single-electron lines (SEL) are determined from a minimalistic tight-binding model. The lines are represented by a chain of coupled ...quantum wells that can be implemented in a mainstream nanoscale CMOS process technology and tuned electrostatically by DC or AC voltage biases. The obtained results show an essential qualitative difference with two capacitively coupled classical electrical lines. The derived equations and their solutions prove that the two coupled SET lines can create an entanglement between electrons. The correlation function characterizing the correlation/anticorrelation in electron position is introduced both in quantum and classical descriptions of capacitively coupled SELs. The quantum measurement conducted on quantum and classical SELs is described. The difference in quantum and classical ground states can be used as the probe determining the 'quantumness' of the SEL system. The results indicate a possibility of constructing electrostatic (non-spin) coupled qubits that could be used as a building block in a CMOS quantum computer.
A
bstract
This study focuses on hard diffractive events produced in proton-proton collision at LHC exhibiting one intact proton in the final state which can be tagged by forward detectors. We report ...prospective results on the W boson charge asymmetry measured for such events, which allow to constrain the quark diffractive density functions in the Pomeron.
The class-D power amplifier (PA) is commonly implemented in CMOS, but its operating frequency is often limited due to the power loss of parasitic capacitances and the lower transition frequency of ...the PMOS transistor. In this brief we demonstrate edge-combining frequency-multiplication embedded directly in the output-stage, allowing higher-frequency operation of the class-D PA, while maintaining similar performance to a lower-frequency PA. A 65nm CMOS prototype achieves output power and system efficiency of 22.3dBm and 30.2%, respectively. The prototype is tested with a D-BPSK signal and achieves an EVM of 2%-rms. Although the prototype was not embedded with amplitude modulation capability, it can be readily adapted for such operation using switched-capacitor PA techniques.
A novel technique for mitigation of self interference in a highly integrated SoC transmitter is presented. The interference originates from the internal power amplifier (i.e., aggressor) that leads ...to injection pulling of the local RF oscillator (i.e., victim). The characteristic of injection pulling was found to be dependent on the AM signal applied to the power amplifier. A hypothesis describing the mechanism of injection pulling of the local oscillator is presented. A mathematical model is developed to study the characteristics of this self interference verified then by measurements. Based on this model, a digitally controlled delay circuit is proposed and implemented in a digital polar GSM/EDGE transmitter that makes the system less susceptible to injection pulling through automatic phase adjustment between the aggressor and the victim. Compliant EVM and spectrum performance is measured on SoC fabricated in 65-nm CMOS showing the effectiveness of the proposed solution.
A
bstract
The MoEDAL experiment is designed to search for magnetic monopoles and other highly-ionising particles produced in high-energy collisions at the LHC. The largely passive MoEDAL detector, ...deployed at Interaction Point 8 on the LHC ring, relies on two dedicated direct detection techniques. The first technique is based on stacks of nucleartrack detectors with surface area ~18m
2
, sensitive to particle ionisation exceeding a high threshold. These detectors are analysed offline by optical scanning microscopes. The second technique is based on the trapping of charged particles in an array of roughly 800 kg of aluminium samples. These samples are monitored offline for the presence of trapped magnetic charge at a remote superconducting magnetometer facility. We present here the results of a search for magnetic monopoles using a 160 kg prototype MoEDAL trapping detector exposed to 8TeV proton-proton collisions at the LHC, for an integrated luminosity of 0.75 fb
–1
. No magnetic charge exceeding 0:5
g
D
(where
g
D
is the Dirac magnetic charge) is measured in any of the exposed samples, allowing limits to be placed on monopole production in the mass range 100 GeV≤ m ≤ 3500 GeV. Model-independent cross-section limits are presented in fiducial regions of monopole energy and direction for 1
g
D
≤ |
g
| ≤ 6
g
D
, and model-dependent cross-section limits are obtained for Drell-Yan pair production of spin-1/2 and spin-0 monopoles for 1
g
D
≤ |
g
| ≤ 4
g
D
. Under the assumption of Drell-Yan cross sections, mass limits are derived for |
g
| = 2
g
D
and |
g
| = 3
g
D
for the first time at the LHC, surpassing the results from previous collider experiments.
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