Electronic noses have potential applications in daily life, but are restricted by their bulky size and high price. This review focuses on the use of chemiresistive gas sensors, metal-oxide ...semiconductor gas sensors and conductive polymer gas sensors in an electronic nose for system integration to reduce size and cost. The review covers the system design considerations and the complementary metal-oxide-semiconductor integrated technology for a chemiresistive gas sensor electronic nose, including the integrated sensor array, its readout interface, and pattern recognition hardware. In addition, the state-of-the-art technology integrated in the electronic nose is also presented, such as the sensing front-end chip, electronic nose signal processing chip, and the electronic nose system-on-chip.
This letter presents an upgraded winner‐take‐all (WTA) circuit that is capable of operating under low‐voltage supplies. The proposed circuit re‐configures the basic loop of a conventional WTA through ...an auxiliary transistor to decrease the dropped voltage across the tail current. This reconfiguration creates an additional biasing voltage providing more adjustability. Moreover, the new feedback path decreases the delay compared to the conventional WTA. Both conventional and proposed WTAs were fabricated in the TSMC 0.18 μm CMOS technology. The experimental results show a 29.4 and 33.2 μs reduction in rising and falling times, respectively, for the proposed WTA under a supply voltage of 0.3 V.
► In this work, the emerging sensor-based methodologies for H2S analysis are explored. ► The common sensor types are grouped by their material type and/or sensing principle. ► The efficacy of ...different sensors is evaluated in terms of QA for real world application. ► Discussion is provided with respect to their advantages, limitations, and future prospects.
We review sensor-based methods commonly employed for monitoring hydrogen sulfide (H2S), and recent developments in H2S-sensing instrumentation.
We evaluate the basic quality-assurance parameters of different sensor types for quantifying H2S in terms of major operational criteria (e.g., response time, limit of detection, common operating range of concentrations, and stability). We also describe the applicability of these sensor-based methods with respect to practicality in various environmental settings. Finally, we highlight the limitations and the future prospects of these sensor-based methods.
Computation-in-memory (CIM) is a promising candidate to improve the energy efficiency of multiply-and-accumulate (MAC) operations of artificial intelligence (AI) chips. This work presents an static ...random access memory (SRAM) CIM unit-macro using: 1) compact-rule compatible twin-8T (T8T) cells for weighted CIM MAC operations to reduce area overhead and vulnerability to process variation; 2) an even-odd dual-channel (EODC) input mapping scheme to extend input bandwidth; 3) a two's complement weight mapping (C2WM) scheme to enable MAC operations using positive and negative weights within a cell array in order to reduce area overhead and computational latency; and 4) a configurable global-local reference voltage generation (CGLRVG) scheme for kernels of various sizes and bit precision. A 64 × 60 b T8T unit-macro with 1-, 2-, 4-b inputs, 1-, 2-, 5-b weights, and up to 7-b MAC-value (MACV) outputs was fabricated as a test chip using a foundry 55-nm process. The proposed SRAM-CIM unit-macro achieved access times of 5 ns and energy efficiency of 37.5-45.36 TOPS/W under 5-b MACV output.
This paper presents a low-power class-AB second-generation voltage conveyor (VCII) based on a new high-drive flipped voltage follower (FVF) circuit. The proposed FVF cell establishes an additional ...negative feedback loop to enhance the driving capability of the VCII. This improvement ensures a very low output impedance and guarantees the accuracy of the circuit. Since the VCII is configured using two of the proposed FVF cells, it benefits from a simple structure, very low impedance at Y and Z terminals, high impedance at X terminal, and high accuracy in current and voltage conveying. In addition, the driving capability of the VCII is several tens of times larger than its biasing current. The circuit was fabricated using TSMC <inline-formula> <tex-math notation="LaTeX">0.18~\mu </tex-math></inline-formula>m CMOS technology occupying a silicon area of <inline-formula> <tex-math notation="LaTeX">121.5~\mu </tex-math></inline-formula>m <inline-formula> <tex-math notation="LaTeX">\times 123.3~\mu </tex-math></inline-formula>m. Experimental results at a supply voltage of ±0.9 V show bandwidths of 155 MHz and 55.3 MHz for voltage and current transfer functions, respectively, while a static power of <inline-formula> <tex-math notation="LaTeX">342~\mu </tex-math></inline-formula>W is consumed. The impedances at Y, Z and X terminals were measured by <inline-formula> <tex-math notation="LaTeX">0.2\Omega </tex-math></inline-formula>, <inline-formula> <tex-math notation="LaTeX">0.3\Omega </tex-math></inline-formula>, and 146 k<inline-formula> <tex-math notation="LaTeX">\Omega </tex-math></inline-formula>, respectively.
Conventional physics-based memristor device modeling methods highly rely on human expertise, which results in a long development period. To address the aforementioned challenges, we propose a new ...generalized memristor (GEM) device modeling framework based on the artificial neural network (ANN) technique, which has a minimum dependency on the underlying physics, resulting in a fast turn-around development time for customized memristor devices. GEM framework models the switching and conducting behaviors of the memristor devices separately, avoiding the signal-dependence issue in the prior time-series data modeling method. The result of the GEM framework is a compact model that supports general-purpose circuit simulators. Experimental results show that our compact model achieves a ratio of root-mean-square error to peak-to-peak (RMSE/PP) of 3.6% compared to the physics-based device model. Performance analysis of memristor-based logic and memristor crossbar circuits are conducted to demonstrate the effectiveness of our proposed GEM framework for the design and analysis of memristor-based circuits.
In this brief, two current generator circuits are used to design a self-biasing transconductance amplifier. The current generators are configured using two n-channel and p-channel cascode current ...mirrors by which a high input dynamic range is achieved. Since such a topology creates positive feedback, the transconductance of the circuit is also increased causing higher performance. To ensure the stability of the circuit, constant current sources can be paralleled with the current mirror topologies, which of course are implemented using input drivers. Therefore, two n-channel and p-channel input differential pairs are added to the current generator circuits by which not only a rail-to-rail operation is achieved but also the amplifier is stabilized. The proposed circuit was fabricated in the TSMC 0.18-<inline-formula> <tex-math notation="LaTeX">\mu</tex-math> </inline-formula>m CMOS process with a silicon area of 54.1 <inline-formula> <tex-math notation="LaTeX">\times</tex-math> </inline-formula> 71 <inline-formula> <tex-math notation="LaTeX">\mu </tex-math> </inline-formula>m. Under a 1.8-V supply voltage, the experimental results showed a high input common-mode range (ICMR), while a gain bandwidth (GBW) of 83.9 MHz was measured for a capacitive load of 2 <inline-formula> <tex-math notation="LaTeX">\times</tex-math> </inline-formula> 6 pF. In addition, a dc gain and a slew rate (SR) of 68.4 dB and 71.7 V/ <inline-formula> <tex-math notation="LaTeX">\mu</tex-math> </inline-formula>s, respectively, were achieved.
Previous SRAM-based computing-in-memory (SRAM-CIM) macros suffer small read margins for high-precision operations, large cell array area overhead, and limited compatibility with many input and weight ...configurations. This work presents a 1-to-8-bit configurable SRAM CIM unit-macro using: 1) a hybrid structure combining 6T-SRAM based in-memory binary product-sum (PS) operations with digital near-memory-computing multibit PS accumulation to increase read accuracy and reduce area overhead; 2) column-based place-value-grouped weight mapping and a serial-bit input (SBIN) mapping scheme to facilitate reconfiguration and increase array efficiency under various input and weight configurations; 3) a self-reference multilevel reader (SRMLR) to reduce read-out energy and achieve a sensing margin 2<inline-formula> <tex-math notation="LaTeX">\times </tex-math></inline-formula> that of the mid-point reference scheme; and 4) an input-aware bitline voltage compensation scheme to ensure successful read operations across various input-weight patterns. A 4-Kb configurable 6T-SRAM CIM unit-macro was fabricated using a 55-nm CMOS process with foundry 6T-SRAM cells. The resulting macro achieved access times of 3.5 ns per cycle (pipeline) and energy efficiency of 0.6-40.2 TOPS/W under binary to 8-b input/8-b weight precision.
Many artificial intelligence (AI) edge devices use nonvolatile memory (NVM) to store the weights for the neural network (trained off-line on an AI server), and require low-energy and fast I/O ...accesses. The deep neural networks (DNN) used by AI processors 1,2 commonly require p-layers of a convolutional neural network (CNN) and q-layers of a fully-connected network (FCN). Current DNN processors that use a conventional (von-Neumann) memory structure are limited by high access latencies, I/O energy consumption, and hardware costs. Large working data sets result in heavy accesses across the memory hierarchy, moreover large amounts of intermediate data are also generated due to the large number of multiply-and-accumulate (MAC) operations for both CNN and FCN. Even when binary-based DNN 3 are used, the required CNN and FCN operations result in a major memory I/O bottleneck for AI edge devices.
Recent brain emulation engines have been configured using thousands of neurons and billions of synapses. These components make a significant impact on the whole system in terms of power consumption ...and silicon area. In this work, several upgraded neuromorphic circuits are used to configure an efficient and compact spike-based learning control module that is capable of operating under ultralow-voltage supplies offering a low energy consumption per spike. In this way, a conductance-based silicon neuron is developed using the simplest highly efficient analog circuits. Moreover, an upgraded winner-take-all (WTA) circuit is used to form a low-voltage multi-threshold current comparator to determine whether to increase or decrease the synaptic weight. Other components such as low-speed amplifier, differential pair integrator (DPI)-based synapse, and weight update controller are designed such that they properly operate under a 0.5V supply voltage. Simulation results in TSMC 0.18 <inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula> CMOS process show an energy consumption of 2.5 pJ for the upgraded learning control module, while its stop-learning mechanism improves the performance of the system by avoiding overfitting.
PDF
