Multiprocessor Systems-on-Chips Jerraya, Ahmed; Tenbunen, Hannu; Wolf, Wayne
Computer (Long Beach, Calif.),
07/2005, Letnik:
38, Številka:
7
Journal Article
Recenzirano
Single processors may be sufficient for low-performance applications that are typical of early microcontrollers, but an increasing number of applications require multiprocessors to meet their ...performance goals.PUBLICATION ABSTRACT
This paper presents an energy detection Impulse Radio Ultra-Wideband (IR-UWB) receiver for Radio Frequency Identification (RFID) and Wireless Sensor Networks (WSN) applications. An ...Application-Specific Integrated Circuit (ASIC) consisting of a 3-5 GHz analog front-end, a timing circuit and a high speed baseband controller is implemented in a 90 nm standard CMOS technology. A Field-Programmable Gate Array (FPGA) is employed as a reconfigurable back-end, enabling adaptive baseband algorithms and ranging estimations. The proposed architecture is featured by high flexibility that adopts a wide range of pulse rate (512 kHz-33 MHz), processing gain (0-18 dB), correlation schemes, synchronization algorithms, and modulation schemes (PPM/OOK). The receiver prototype was fabricated and measured. The power consumption of the ASIC is 16.3 mW at 1 V power supply, which promises a minimal energy consumption of 0.5 nJ/bit. The whole link is evaluated together with a UWB RFID tag. Bit error rate (BER) measurement displays a sensitivity of -79 dBm at 10 Mb/s with 10 -3 BER achieved by the proposed receiver, corresponding to an operation distance over 10 meters under the FCC regulation.
Memory-Efficient On-Chip Network With Adaptive Interfaces Daneshtalab, M.; Ebrahimi, M.; Liljeberg, P. ...
IEEE transactions on computer-aided design of integrated circuits and systems,
2012-Jan., 2012-01-00, 20120101, 2012, Letnik:
31, Številka:
1
Journal Article
Recenzirano
To achieve higher memory bandwidth in network-based multiprocessor architectures, multiple dynamic random access memories can be accessed simultaneously. In such architectures, not only resource ...utilization and latency are the critical issues but also a reordering mechanism is required to deliver the response transactions of concurrent memory accesses in-order. In this paper, we present a memory-efficient on-chip network architecture to cope with these issues efficiently. Each node of the network is equipped with a novel network interface (NI) to deal with out-of-order delivery, and a priority-based router to decrease the network latency. The proposed NI exploits a streamlined reordering mechanism to handle the in-order delivery and utilizes the advance extensible interface transaction-based protocol to maintain compatibility with existing intellectual property cores. To improve the memory utilization and reduce the memory latency, an optimized memory controller is integrated in the presented NI. Experimental results with synthetic test cases demonstrate that the proposed on-chip network architecture provides significant improvements in average network latency (16%), average memory access latency (19%), and average memory utilization (22%).
New models for estimating delay and noise in VLSI circuits, based on closed form expressions for the first and second moment of the impulse response in coupled RC trees are reported. The effect of ...crosstalk on delay and noise can be accurately estimated with a complexity only marginally higher than the Elmore delay.
Remote healthcare monitoring has exponentially grown over the past decade together with the increasing penetration of Internet of Things (IoT) platforms. IoT-based health systems help to improve the ...quality of healthcare services through real-time data acquisition and processing. However, traditional IoT architectures have some limitations. For instance, they cannot properly function in areas with poor or unstable Internet. Low power wide area network (LPWAN) technologies, including long-range communication protocols such as LoRa, are a potential candidate to overcome the lacking network infrastructure. Nevertheless, LPWANs have limited transmission bandwidth not suitable for high data rate applications such as fall detection systems or electrocardiography monitoring. Therefore, data processing and compression are required at the edge of the network. We propose a system architecture with integrated artificial intelligence that combines Edge and Fog computing, LPWAN technology, IoT and deep learning algorithms to perform health monitoring tasks. In particular, we demonstrate the feasibility and effectiveness of this architecture via a use case of fall detection using recurrent neural networks. We have implemented a fall detection system from the sensor node and Edge gateway to cloud services and end-user applications. The system uses inertial data as input and achieves an average precision of over 90% and an average recall over 95% in fall detection.
This paper reports an analogy between on-chip signaling and digital communication over a band-limited channel. This analogy has been used to design a scheme for low-power, on-chip signaling, robustly ...resistant to power-supply noise. The technique uses multilevel, current-mode signaling as its core. The number of levels is determined by estimating the bandwidth of the wire. A closed-form expression has been presented here describing the bandwidth of a wire modeled as a first-order RLC circuit. An algorithm is presented for computing the levels of the current given target bit rate, bit-error rate, and wire characteristics. Simulation results using HSPICE from Avant! show that the algorithm for computing the wire bandwidth presented here has an average error of less than 10%. Experimental results on a set of benchmark signaling problems implemented in a 0.25-/spl mu/m 2.5-V CMOS process, show that using four levels of current instead of the standard two levels allows a two-fold reduction in the power and a reduction of 1.4 times the area.
The cooperation of multiple robots towards a common goal requires a certain spatial distribution, or formation configuration, of the agents in order to succeed. Centralized controllers that have ...information about the absolute or relative positions of all agents, or distributed approaches using communication to share system-wide information between agents, are able to calculate optimal individual paths. However, this reserves important computational resources as the number of agents in the system increases. We address the problem of distributed formation control with minimal communication and minimal computational power required. The algorithm introduced in this paper progressively generates a directed path graph to uniquely assign formation positions to all agents. The benefits of the proposed algorithm compared to previous include the need for one-way communication only, low computational complexity, ability to converge without any a priori assignments under certain geometric conditions and need for limited sensing information only. The algorithm can be deployed to computationally constrained devices, enabling its deployment in robots with simpler hardware architectures. The ability to converge and distributively assign positions, or roles, with only one-way communication makes this algorithm robust during deployment, at which time all agents are equivalent and anonymous. Moreover, we account for limited communication and sensing range, and agents only need to have information about other agents in their vicinity in order to make decisions. Communication is simple and allows for scalability without an impact on performance or convergence latency, with a linear dependence on the number of agents. Agents only need to broadcast their status to other neighboring agents and do not reply any message. Finally, this algorithm enables almost-arbitrary configurations. The main limitation for the choice of formation configuration is that all pairs of points forming an edge in the polygonal line defining the boundary of the convex hull must be within sensing range.
In this paper, energy dissipation in resistance-inductance-capacitance (RLC) current-mode signaling is modeled. The energy dissipation is derived separately for driver, wire, and receiver ...termination. The effects of rise time and clock cycle are included. A realizable Π-model for the driving-point impedance of an RLC current-mode transmission line is derived. The output current of an RLC current-mode transmission line is also derived. The model is extended to multiple parallel coupled interconnects with inductive and capacitive coupling between them. The model is verified by comparing it to HSPICE in 65-nm technology and applied to differential current-mode signaling.
This paper describes LP-DSM, which is an algorithm used for efficient library characterization in high-level power estimation. LP-DSM characterizes the power consumption of building blocks using the ...entropy of primary inputs and primary outputs. The experimental results showed that over a wide range of benchmark circuits implemented using full custom design in 0.35-/spl mu/m 3.3 V CMOS process the statistical performance (mean and maximum error) of LP-DSM is comparable or sometimes better than most of the published algorithms. Moreover, it was found that LP-DSM has the lowest prediction sum of squares, which makes it an efficient tool for power prediction. Furthermore, the complexity of the LP-DSM is linear in relation to the number of primary inputs (O(NI)), whereas state of the art published library characterization algorithms have a complexity of O(NI/sup 2/).
The development of autonomous vehicles has seen considerable advances over the past decade. However, specific challenges remain in the area of autonomous waterborne navigation. Two key aspects in ...autonomous surface vehicles are sensor calibration and segmentation of water surface. Cameras and other sensors in a car or drone can be installed accurately in a specific position and orientation. In a large vessel, this is not always possible, as sensors might be installed around the vessel or on masts. Taking advantage of the medium in which these vehicles operate, the water plane can be used as a reference for different sensors to calibrate their orientation. This allows more accurate localization of obstacles of objects. State-of-the-art deep learning techniques have been successfully applied for water surface segmentation in open sea. However, in other environments such as small rivers or lakes with still waters, a different approach might enable more accurate water surface estimation. We propose a method to estimate the water plane based on the detection of local symmetry planes that naturally occur when objects are reflected in the water. By using a point cloud generated with a stereo camera, we are able to accurately estimate the water level and, at the same time, calibrate the camera position and improve the localization of obstacles. We assume that an approximate position and orientation of the camera is known with respect to the sea level. We demonstrate the efficiency of our method with data obtained in the Aura river, Finland, with our prototype vessel facing both the riverside and the center of the river.
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