Traditional pulse oximeters rely on the use of red and infrared LEDs and a photodiode for measuring transmittance between tissues and estimate the functional oxygen saturation. Currently, studies are ...being made for the development of multiwavelength pulse oximeters in order to increase accuracy and to estimate the presence of other compounds such as carboxyhemoglobin or methemoglobin. The purpose of this work is the characterization and implementation of a pulse oximeter with a Buried Quad Junction photodetector (BQJ), which can reduce both: the number of photodetectors and the area needed for multiwavelength pulse oximetry. With this type of photodetector, it is also possible to continuously estimate oxygen saturation without the need of pulsating LEDs.
Fibrosis represents an open issue for medium to long-term active implants given that this biological medium surrounds the stimulation electrodes and can impact or modify the performances of the ...system. For this reason, Embedded Impedance Spectroscopy techniques has been investigated these last years to sense the fibrosis. The following article introduces a new paradigm for Electrochemical Impedance Spectroscopy (EIS) derived from multi-carrier digital communication methods. Due to its properties of flat spectrum and fast generation the Orthogonal-Frequency Division Multiplexing (OFDM) technique for EIS seems to be a real alternative to traditional ones. This article focuses on this approach and defines its performances on gold electrodes used for in-vitro experiments. An embedded implementation is also presented. This designed prototype allows to measure a medium with an error between 2% and 3%, when stimulating with a 16 or 32 tones multitone signal and a sampling frequency of 12KHz.
In this article, our concern is the early diagnosis of colorectal cancer from a computeraided detection point of view in order to help physicians in their diagnosis during the gold standard ...examination: optical video colonoscopy. Since many years, some methods and materials have been developed to reduce the polyp miss rate and to improve detection capabilities. Nevertheless, the real challenge lies in the real-time use of these methods. In this context, more precisely, we focus our attention on the hardware implementation of a previous method we recently introduced in the literature for real-time detection of colorectal polyps, lesions that may degenerate into cancer. This implementation is subject to three performance criteria: real-time processing capabilities, detection rate and necessary computational resources. Six different platforms were tested and compared. If we noticed that only workstation computers are able to perform the detection with a good tradeoff between the three aforementioned criteria, possibilities of architecture optimizations are also identified and discussed in order to achieve real-time performance on platforms with low available computational resources like Raspberry Pi for instance. This latter issue is of major importance for possible integration of the detection algorithm inside smallconnected object like videocapsule, a promising alternative to standard colonoscopy.
A wireless and portable system, consisting in an electronic board and a computer software graphical interface, is presented in this article as a feasible way to do in-vitro electric bioimpedance ...spectroscopy of cells. It is designed to work inside a culture chamber performing impedance measurement in the frequency range of 64Hz to 200KHz. The board is equipped with a Bluetooth Low Energy (BLE) module allowing it to be wirelessly controlled. The software interface (also called ISMI) is coded with all required functionalities to manage the parameters of the board such as start frequency and sweep, measuring intervals, data acquisition and visualization and also a function to perform automatic measuring between desired time intervals during whole day for many days. In addition, the electrodes used for the measurements of cells are characterized giving an impedance magnitude between 103 to 105 ohms in a frequency range of 300Hz to 100KHz and a maximum voltage without considerable electrode deterioration of 120mVpeak. This information is used in the calibration of the ISMI system giving a measurement accuracy above 98% when compared with simulation results and with a reference instrument. The proposed system is an introductory step in the study of cells related to fibrous tissue induced by implants showing to be a viable and reproducibility-improving approach for such analysis. This first prototype provides information regarding the requirements for the design of an integrated version for embedded applications.
Tri-state inverter based DCO are emerging as an attractive circuit for the implementation of fully digital PLL. In this paper, we first introduce an analytical expression of the tuned period as a ...function of design and technology parameters. Then, we propose a sizing methodology for the CMOS implementation of a tri-state inverter based DCO. Finally, we applied this methodology to the design of such a DCO. We achieved an average error of 5.4% for our analytical expression compared to simulation results. In conclusion, we showed that our analytical expression and sizing methodology are directly applicable to the design of tri-state inverter based DCO.
A self-sufficient Giga-Hertz digitally controlled ring oscillator for clock distribution network is presented in this paper. It features a high supply insensitivity in order to mitigate the ...additional jitter due to supply noise. This is achieved by inducing a mutual compensation between the oscillation frequency parameters that are affected by the supply voltage variations. The proposed method can be easily implemented and takes advantage of the deep sub-micrometer effects peculiar to topical CMOS technologies. We demonstrate by simulations that this approach remains efficient over process variations despite the reliability issue of short channel MOS transistors.
This paper presents an FPGA platform for the design and study of network of coupled All-Digital Phase Locked Loops (ADPLLs), destined for clock generation in large synchronous System on Chip (SoC). ...An implementation of a programmable and reconfigurable 4×4 ADPLL network is described. The paper emphasizes the difference between the FPGA and ASIC-based implementation of such a system, in particular, implementation of digitally controlled oscillators and phase-frequency detector. The FPGA-implemented network allows studying complex phenomena related to coupled ADPLL operation and exploiting stability issues and nonlinear behavior. A dynamic setup mechanism has been proposed for the network, allowing selecting the desirable synchronized state. Experimental results demonstrate the global synchronization of network and performance of the network for different configurations.
L'intégration d'un plus grand nombre de fonctions sur des circuits intégrés plus rapides à chaque nouvelle génération. Malheureusement, elles ont rendu la tâche des concepteurs plus difficile, avec ...notamment la montée de la puissance consommée et des temps de propagation des signaux à travers la puce. La distribution de l'horloge, assurant le synchronisme des opérations du circuit, en est l'élément le plus symptomatique. La génération distribuée de l'horloge apparaît comme une alternative aux solutions classiques. Elle repose sur la mise en place d'un réseau de N oscillateurs géographiquement distribués sur l'ensemble de la puce. Chaque oscillateur génère localement une horloge pour la zone de la puce dans laquelle il se trouve. La phase d'une horloge est accordée sur celle de ces proches voisines. Ainsi, l'horloge n'a plus à parcourir de long chemin. Toutefois, les performances du circuit d'horloge sont liées, non pas à un, mais à N oscillateurs évoluant dans un environnement hostile (variations de l'alimentation, de la température, etc.). Aussi, les travaux de cette thèse portent sur la conception d'un oscillateur contrôlé numériquement. Plus précisément, notre problématique est : " Comment concevoir un DCO (Digitally Controlled Oscillator) robuste soumis à l'environnement hostile d'un SoC en technologie CMOS submicronique ? ". Pour répondre à cette question, nous proposons, dans un premier temps, la modélisation d'une topologie d'oscillateur contrôlé numériquement ; le but étant de déterminer sa pertinence quant à notre application d'horlogerie. Comme cette dernière est émergente, il n'y a à l'heure actuelle aucune théorie la caractérisant. A travers notre analyse, nous mettons en évidence ses faiblesses et la nécessité de lui adjoindre des circuits de protection. De ce fait, les performances du circuit d'horloge ne sont plus seulement dépendantes de l'oscillateur, mais aussi des dispositifs mis en place pour le protéger des agressions des circuits environnants. Ce constat a motivé le développement d'une alternative qui ne serait pas soumise aux mêmes contraintes. Nous proposons finalement un oscillateur contrôlé numériquement robuste à la fois contre les variations de l'alimentation et de la température. Cet oscillateur est conçu à partir de blocs analogiques connus et bien décrits par la littérature. Pour limiter l'influence de la tension d'alimentation et de la température à laquelle évolue l'oscillateur, nous tirons profit des effets de canal court propres aux technologies submicroniques.
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