In this letter, we propose a novel wideband subharmonically pumped fully differential I-Q resistive mixer architecture, which eliminates the necessity for on-chip dc-blocking capacitors to integrate ...IF amplifiers. The proposed differential subharmonic mixer topology is verified by presenting a CMOS millimeter-wave monolithic integrated circuit (MMIC), which includes the mixer and two on-chip differential IF amplifiers at the mixer's I- and Q-channels. The 3-dB IF frequency bandwidth is measured from 0.01 to 5 GHz with a peak conversion gain (CG) of −2 dB and an image rejection ratio (IRR) of more than 25 dB over the IF frequency range. The proposed mixer covers the input signal (RF) frequency from 170 to 185 GHz. The mixer has also been tested with an on-chip voltage-controlled oscillator (VCO) and shows −4.7-dB CG with a 3-dB IF bandwidth from 0.01 to 4.5 GHz.
A compact second harmonic 180 GHz I/Q balanced resistive mixer is realized in a 32-nm SOI CMOS technology for atmospheric remote sensing applications. The MMIC further includes two on-chip IF ...amplifiers at the mixer's I and Q channels. A conversion gain of +8 dB is achieved with 74 mW of dc power consumption using a 1.2 V supply. The measured IF frequency range is from 1 to 10 GHz. The mixer achieves a 20 dB imagerejection (IR) ratio with an LO input power of +4 dBm. The chip size is 0.75 mm 2 including probing pads.
This paper describes a wide-band receiver designed to be connected directly to a single-ended non-50 ohm antenna. The receiver is based on a four-phase mixer-first architecture and it includes an ...on-chip transformer balun. Reconfigurability in the balun extends the low-end operation band by 300 MHz. This design demonstrates that with an on-chip balun it is possible to achieve comparable performance to a similar receiver with an external high-performance balun. The receiver is implemented in 65-nm CMOS and it operates in 0.8-3 GHz band with 40 dB gain and 7 dB noise figure.
This paper presents a fully integrated 40-GHz transceiver designed for 2 Gbit/s short-range chip-to-chip communication link. The proposed architecture includes both the transmitter and the receiver ...and is optimized for on–off-keying modulation scheme. The transceiver design includes two variants, which can drive either a planar on-chip antenna or wire-bonded off-chip antenna. The performance comparison of these is given in the paper. A compact and energy-efficient technique has been adopted by directly modulating the oscillator in the transmitter. The receiver uses a self-mixing topology followed by transimpedance amplifier and a limiter chain. The detailed circuit descriptions as well as design trade-offs with simulation results in 65 nm CMOS are given. In addition, an example design modification to extend the modulation to 4-level amplitude shift keying is presented.
A scalable low-voltage signaling (SLVS) serial link transmitter for MIPI M-PHY is presented in this paper. It delivers 200–400 mV pp signals at date rates of 1.25–5.8 Gbps. The integrated circuit ...entity consists of the actual SLVS driver, an ADPLL-based clock synthesizer with a frequency multiplier, and an internal test signal generator with pseudo-random binary sequences. The circuit has been fabricated in a 40-nm CMOS process. The overall active die area is 0.2 mm
2
, while the actual driver occupies only 190 μm
2
. In this work it was confirmed that a low-power SLVS driver meets the stringent common-mode noise generation limits set for serial interfaces used in mobile devices. Noise power density remains below −138 dBm/Hz at all data rates. Total power consumption of the transmitter is kept low by utilizing dynamic CMOS pre-drivers and a low drop-out voltage regulator. It achieves power efficiency of 0.44–1.4 mW/Gbps with external clock and 2.6–4.7 mW/Gbps with clock synthesizer.
This paper presents a clock generator for a MIPI M-PHY serial link transmitter, which includes an ADPLL, a digitally controlled oscillator (DCO), a programmable multiplier, and the actual serial ...driver. The paper focuses on the design of a DCO and how to enhance the frequency resolution to diminish the quantization noise introduced by the frequency discretization. As a result, a 17-kHz DCO frequency tuning resolution is demonstrated. Furthermore, implementation details of a low-power programmable 1-to-2-or-4 frequency multiplier are elaborated. The design has been implemented in a 40-nm CMOS process. The measurement results verify that the circuit provides the MIPI clock data rates from 1.248 GHz to 5.83 GHz. The DCO and multiplier unit dissipates a maximum of 3.9 mW from a 1.1 V supply and covers a small die area of 0.012 mm 2 .
The multicarrier receiver IC described in this paper receives four adjacent WCDMA channels simultaneously in order to reduce the component count of a base-station. The receiver uses low-IF ...architecture and it is fabricated with a 0.25-mum SiGe BiCMOS process to meet the high-performance requirements set by the base-station application. The receiver includes a dual-input low-noise amplifier (LNA), quadrature mixers, a local-oscillator (LO) divider, IIP2 calibration circuits, 10-MHz low-pass filters, and ADC buffers. The receiver noise figures, measured over the downconverted WCDMA channels centered at 2.5-MHz and 7.5-MHz intermediate frequencies, are 3.0 dB and 2.6 dB, respectively. The receiver achieves 47-dB voltage gain and -12-dBm out-of-band IIP3 and consumes 535mW from a 2.5-V supply
This paper focuses on the design and measurements of low-noise amplifiers (LNA) targeted for WCDMA base-station applications. In addition, various gain control techniques and the accuracy in noise ...measurements have been analyzed. Two different LNA designs are presented. Both LNAs can be operated in two gain modes, which are optimized for different base-station configurations. Both designs are implemented using the same 0.25-μm SiGe BiCMOS process, and both designs achieve the NF of 1 dB and IIP3 of −5 dBm in high gain mode.
This paper presents a 30-39 GHz 2Gbit/s OOK modulator targeted for chip-to-chip communications. The design is based on a 10 to 13 GHz ring oscillator with three times frequency multiplier, and an ...embedded 2 Gbit/s data feed. The detailed circuit description as well as analysis to estimate the effect of component mismatches to both ring oscillator and frequency multiplier performance is given in this paper.
This paper describes an all-digital phase-locked loop based clock generator for a MIPI M-PHY serial link transmitter. The paper focuses on ADPLL phase accumulator speed optimization, PVT calibration, ...loop type changing criteria and power saving in phase digitization process. The experimental circuit is implemented in 40 nm CMOS and generates the MIPI M-PHY defined frequencies from 1.2 GHz to 5.8 GHz.
