The insertable B-Layer upgrade of the ATLAS pixel detector forsees the installation of a fourth pixel layer close to the beam pipe inside the current ATLAS pixel detector. A new readout chip (FE-I4) ...has been developed to match the increased requirements in terms of radiation hardness and hit occupancy. A new USB-based test system for ATLAS hybrid pixel detectors (USBpix) will serve as test bench for this new readout chip generation. The performance of USBpix is compared to the performance of the TPLL/TPCC system, used for testing the ATLAS pixel detector readout chips FE-I3 and modules. The main differences between the FE-I3 and the FE-I4 are summarized from the point of view of the test systems and the implementation of the main blocks for chip configuration, data storage and histogramming in the USBpix FPGA firmware for both chip generations is discussed. Results of the first measurements which were done using the FE-I4 emulator developed for debugging purposes are discussed.
Reducing material in silicon trackers is of major importance for a good detector performance overall, and poses a big challenge in the development of the detectors. To match the low material ...desirable for trackers in High Energy Physics experiments at upgraded luminosities, special techniques have to be developed to address the main sources of material, i.e. mechanical structure and services, and to prevent new significant contributions to the detector material coming for instance from larger Front-End chips. In this framework three methods are developed to reduce the material added by services and electronics: (1) serial powering, (2) light weight aluminum flex cables and Through Silicon Vias, and (3) thin Front-End chips. The methods are presented in this paper using the upgrades of the ATLAS pixel detector as an example of application.
The prospects for the measurement of the tensor structure of the vertex between a standard model Higgs boson and two weak gauge bosons using the distribution of the azimuthal angles between the two ...tagging jets in the weak boson fusion channel are studied in a Monte Carlo analysis using the fast simulation of the ATLAS detector. The decay channels H→τ+τ-→ll+4ν, H→τ+τ-→lh+3ν at mH=120 GeV and H→W+W-→llνν at mH=160 GeV are used in the analysis. For a standard model Higgs boson it is found that purely anomalous couplings are expected to be excluded at a confidence level corresponding to 2σ or more at mH=120 GeV and more than 5σ at mH=160 GeV from 30 fb-1 of data. With a value of 1 roughly reproducing the standard model cross section for a purely anomalous coupling, the standard deviation in a measurement of a contribution of a CP even anomalous coupling in addition to the standard model coupling is estimated to be 0.20 at mH=120 GeV and 0.09 at mH=160 GeV.
The charge collection properties of Cadmium–Telluride (CdTe) and Cadmium–Zinc–Telluride (CZT) in comparison with Silicon (Si) are presented using the transient-current technique (TCT) where the ...current pulses are generated by
α
-particles emitted from an
241Am source. From the recorded current pulse shapes, the charge collection efficiency, the charge carrier mobility and the electric field distribution inside the detectors are extracted. In particular, the signals of the compound semiconductors CdTe and CZT are interpreted with respect to the build-up of space–charges in the sensor volume and the subsequent deformation of the electric field. As high-quality CdTe and CZT samples are now commercially available, the knowledge of these material characteristics is of outmost importance for the application of CdTe and CZT in X-ray imaging.
In addition, the paper describes the influence of Ohmic and Schottky contacts on the current pulses in CdTe as well as the effects of polarization, i.e. the time-dependent degradation of the detector signals due to the accumulation of fixed charges within the sensor.
Pixel detectors for charged particles Wermes, N.
Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment,
06/2009, Letnik:
604, Številka:
1
Journal Article
Recenzirano
Odprti dostop
Pixel detectors, as the current technology of choice for the innermost vertex detection, have reached a stage at which large detectors have been built for the LHC experiments and a new era of ...developments, both for hybrid and for monolithic or semi-monolithic pixel detectors is in full swing. This is largely driven by the requirements of the upgrade programme for the superLHC and by other collider experiments which plan to use monolithic pixel detectors for the first time. A review on current pixel detector developments for particle tracking and vertexing is given, comprising hybrid pixel detectors for superLHC with its own challenges in radiation and rate, as well as on monolithic, so-called active pixel detectors, including monolithic active pixels (MAPS) and DEPFET pixels for RHIC and superBelle.
This paper describes the recent development of a gigabit data transmitter for the Belle-II pixel detector (PXD). The PXD is an innermost detector currently under development for the upgraded KEK-B ...factory in Japan. The PXD consists of two layers of DEPFET sensor modules located at 1.8 and 2.2 cm radii. Each module is equipped with three different ASIC types mounted on the detector substrate with a flip-chip technique: (a) SWITCHER for generating steering signals for the DEPFET sensors, (b) DCD for digitizing the signal currents, and (c) DHP for performing data processing and sending the data off the module to the back-end data handling hybrid via similar to 40cm Kapton flex and 12-15 m twisted pair (TWP) cables. To meet the requirements of the PXD data transmission, a prototype of the DHP data transmitter has been developed in a 65-nm standard CMOS technology. The transmitter test chip consists of current-mode logic (CML) drivers and a phase-locked loop (PLL) which generates a clock signal for a 1.6 Gbit/s output data stream from an 80 cm reference clock. A programmable pre-emphasis circuit is also implemented in the CML driver to compensate signal losses in the long cable by shaping the transmitted pulse response. The jitter performance was measured as 25 ps (1 sigma 1 sigma distribution) by connecting the chip with 38 cm flex and 10 m TWP cables.
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