A compact wideband bandpass filter with a wide passband and very‐wide out‐of‐band suppression is presented. The filter is constructed from a central rectangular‐ring resonator with two open stubs ...placed around it symmetrically. In addition, tri‐section stepped‐impedance resonators are symmetrically distributed on both sides of the two open stubs, and two symmetrical funnel‐shaped resonators are included to enhance out‐of‐band suppression. The out‐of‐band performance of filter is very good, with a suppression level greater than 20 dB up to 25.72 GHz. The center frequency of the filter is 5.84 GHz, with a fractional bandwidth of 115.8%. Good agreement between the simulations and measurements validates the design principle.
The L-shaped tunnel field-effect transistor (LTFET) improves current drivability significantly by transforming the path of the band-to-band tunnelling from point-tunnelling to line-tunnelling, but ...meanwhile, the gate-source overlapped structure of LTFET brings about a larger active area of interface trap charges (ITCs). In this paper, the impact of ITCs on LTFET's characteristics is investigated in terms of the electric field, dc, analogue/RF, linearity and transient performance. From TCAD simulation results, it is found that for conventional LTFET, different types of ITCs lead to distinct variations in I–V characteristics, subthreshold swing, transconductance, parasitic capacitances, cut-off frequency, linearity parameters such as $V_{{\rm IP2}}$VIP2, $V_{{\rm IP3}}$VIP3, $I_{{\rm IP3}}$IIP3, and $I_{{\rm MD3}}$IMD3 and the fall propagation delay $({t_{{\rm pHL}}} )$(tpHL). To improve the device stability, heterogeneous gate dielectric (HGD) structure is introduced into LTFET. From comparison results, it is found that benefiting from the improved gate controllability near the tunnelling junction, HGD-LTFET not only improves dc, analogue/RF, linearity and transient performance but also effectively suppresses the variation caused by ITCs thus has better stability. Therefore, HGD-LTFET is a very attractive choice in future low-power and high-frequency applications.
The effects of low-
κ
and high-
κ
spacer were investigated on the novel tunnel dielectric based tunnel field-effect transistor (TD-FET) mainly based upon ultra-thin dielectric direct tunneling ...mechanism. Drive currents consist of direct tunneling current and band-to-band tunneling (BTBT) current. Meanwhile, tunneling position of the TD-FET differs from conventional tunnel-FET in which the electron and hole tunneling occur at intermediate rather than surface in channel (or source-channel junction under gate dielectric). The 2-D nature of TD-FET current flow is also discussed that the on-current is degraded with an increase in the spacer width. BTBT current will not begin to play part in tunneling current until gate voltage is 0.2 V. We clearly identify the influence of the tunneling dielectric layer and spacer electrostatic field on the device characteristics by numerical simulations. The inserted Si
3
N
4
tunnel layer between P+ region and N+ region can significantly shorten the direct and band-to-band tunneling path, so a reduced subthreshold slope (
S
S
) and a high on-current can be achieved. Above all the ambipolar current is effectively suppressed, thus reducing off-current. TD-FET demonstrates excellent performance for low-power applications.
The construction of tax forecasting model is difficult due to its uncertain, non-linear, dynamic and complicated characteristics. It is difficult to describe the non-linear characteristics of tax ...forecasting by traditional methods. In the study, the novel forecasting method based on the combination of support vector machine (SVM) and particle swarm optimization (PSO) is proposed to the tax forecasting. The non-linear relationship in tax forecasting is efficiently represented by support vector machine, and particle swarm optimization is used to select the training parameters of support vector machine. The tax forecasting model is constructed by support vector machine optimized by particle swarm optimization (PSVM) on the basis of research for the proposed forecasting model. The tax forecasting cases are used to testify the forecasting performance of the proposed model. The experimental results demonstrate that the proposed PSVM model has good forecasting performance.
VDMOS integrated in scan driver chip for plasma display panels (PDP) is disclosed in the paper, which is based on the epitaxial Bipolar-CMOS- DMOS (BCD) process. The key considerations during the ...design are proposed here, and abundance simulation and process regulation is done on the structure and parameter optimization, by the testing on the VDMOS parameter and chip parameter, the results is favorable for 170 V PDP scan driver chip, which contributes to the competitive cost efficiency.
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