Modern deep neural networks (DNNs) require billions of multiply-accumulate operations per inference. Given that these computations demand relatively low precision, it is feasible to consider analog ...computing, which can be more efficient than digital in the low-SNR regime. This overview article investigates the potential of mixed analog/digital computing approaches in the context of modern DNN processor architectures, which are typically limited by memory access. We discuss how memory-like and in-memory compute fabrics may help alleviate this bottleneck and derive asymptotic efficiency limits at the processing array level. It is shown that single-digit fJ/op energy efficiencies are feasible for 4-bit mixed-signal arithmetic. In this analysis, special consideration is given to the SNR and amortization requirements of the analog-digital interfaces. In addition, we consider the pros and cons for a variety of implementation styles and highlight the challenge of retaining high compute efficiency for a complete DNN accelerator design.
Switched capacitor (SC) circuits have been widely used for low-power and high-power areas, such as the integration circuit power supply, energy conversion for wearable devices, and power supply for ...data centers and electrical vehicles. The dc-dc conversion, dc-ac inversion, ac-dc rectification, and ac-ac conversion of SC topologies have been explored and discussed. This article provides a review of different topologies, application areas, mathematical models, and control methods for SC circuits. Compared with other review papers on SC converters, this article deeply and comprehensively surveys the topological structure classification and the equivalent circuits. It explores the application fields and the operation performance of SC circuits. The modeling method is presented as the steady-state modeling method and the transient modeling method. It will help to achieve accurate simulation and prediction and lay the foundation for theory analysis. The different mathematical models' construction algorithms and the suitable application range are analyzed in this article. The control methods determine the quality of the output voltage and the output power for SC circuits. They are classified as the linear control methods and the nonlinear control methods. The nonlinear control methods will help to achieve high-quality output voltage or current regulation with low ripples and fast dynamical response speed. The comparison of different topologies, application areas, modeling methods, and control methods is provided and discussed. What is more, the simulation accuracy of different modeling strategies and static and dynamical regulation performance of different control algorithms are presented in this article, respectively. The challenges and opportunities for SC circuits are prospected.
This paper presents research results of voltage gain number control methods of a power electronic resonant zero-current switching dc-dc switched-capacitor (SC) voltage multiplier (SCVM) in a topology ...with fault tolerance capability (FSCVM). The converters operated under the basic switching patterns are constant-voltage-gain dc-dc series-parallel resonant SC converters. However, this paper presents a method for the output voltage regulation by a special switching strategy. A variable voltage gain is made possible by selecting the number of active switching cells, using an appropriate control method. This creates a set of voltage ratio ranges. In addition, the proposed topology and method of control enable a fault-tolerant operation of the FSCVM under various failures of the device. The paper presents an analysis of the concept, simulation results and an experimental verification in a three-cell FSCVM dc-dc resonant boost converter operating at a 200-watt charge. Issues regarding the selection of components related to the problem of inrush currents that can occur during the voltage ratio increase are also analyzed in this paper, and the design for low inrush currents is demonstrated.
High step-up converters are crucial in many power electronic interfaces, including for renewable energy sources. As the result of topological variation of high step-up converters, many topologies ...share similar characteristics. In order to have a clear understanding of an optimized design that makes the best use of components to achieve high gain, it is necessary to devise a generalized comprehension method for high step-up converters. This article presents a novel generalized method for analyzing single-switch step-up converters that can include switched capacitor (SC) cells, a coupled inductor (CI), and/or voltage multiplier cells (VMCs). The proposed method is neither dependent on the position of the CI nor the structure of the VMC, and is not tied to a specific topology. Thus, the proposed generalized method uniquely reveals the unifying theory underlying high step-up converters with any variation of SC/CI/VMC. In order to verify the theoretical analysis, many examples from the literature are investigated. Then, using design tips from the generalized method, a new high step-up converter is designed. A 150-W prototype of the converter shows 97.5% peak efficiency. The proposed converter also compares favorably to other topologies in both a power loss breakdown analysis and a component stress factor analysis.
This article presents a compact <inline-formula> <tex-math notation="LaTeX">2\times </tex-math></inline-formula> time-interleaved switched-capacitor (SC) digital-to-analog converter (DAC) for ...digital-intensive transmitter architectures. To minimize area and to leverage the strengths of FinFET technology, the implementation departs from the traditional current steering approach and consists mainly of inverters and sub-femtofarad SCs. The DAC's architecture is based on parallel charge redistribution and separates level generation, pulse timing, and output power generation. The described 28-GS/s 8-bit prototype design occupies 0.03 mm 2 in 16-nm CMOS and supports up to 0.32-<inline-formula> <tex-math notation="LaTeX">\textrm {V}_{\textrm {pp}} </tex-math></inline-formula> signal swing across its differential 100-<inline-formula> <tex-math notation="LaTeX">{\Omega } </tex-math></inline-formula> load. It achieves an SFDR <inline-formula> <tex-math notation="LaTeX">\geq 37 </tex-math></inline-formula> dB and an IM<inline-formula> <tex-math notation="LaTeX">3\leq -45.6 </tex-math></inline-formula> dBc across the first Nyquist zone while consuming 88 mW from a single 0.8-V supply.
A novel single-switch coupled-inductor switched-capacitor (CISC) high step-up converter is proposed which has a boost-type input structure allowing an improved input current ripple compared to other ...leading CISC converters. This is important for sustainable energy applications, such as photovoltaic (PV) cells and fuel cells where high current ripple can degrade performance or lifetime. Though large input filters can be added between the energy source and the boost converter to smooth a pulsed converter input current, the proposed converter naturally has a more moderate current ripple, reducing the need for additional filtering. With regards to the coupled inductor, the leakage inductor energy is recycled without using an extra clamped circuit, and core utilization is high. The detailed theoretical operation is presented and an experimental prototype (200 W, 36 V to 48 input, 400 V output) achieves a maximum efficiency of 97.1%.
This article presents a reconfigurable single-inductor multi-stage (SIMS) hybrid step-down converter that efficiently provides a wide range of voltage conversion ratios (VCRs) needed for 1-cell ...battery charging across a wide input voltage range of 5-24 V while moving the inductor away from the high-output current path. The inductor is used to couple two synchronous switched-capacitor stages to provide soft charging benefits to each stage. A prototype was implemented in a 0.18 <inline-formula> <tex-math notation="LaTeX">\mu</tex-math> </inline-formula>m bipolar, complimentary metal-oxide semiconductor, double-diffused metal-oxide semiconductor (BCD) process with a die area of 9.4 mm<inline-formula> <tex-math notation="LaTeX">^{2}</tex-math> </inline-formula>. It extends reconfigurable switched-capacitor and merged multi-stage operation concepts to deliver a maximum output current of 5 A and achieves peak efficiencies of 94.8% and 92.4% from 5-and 24-V input supplies, respectively.
This article presents a new step-down hybrid converter topology that uses an input flying inductor and a switched-capacitor network to generate output voltages suitable for charging 1-cell (1S) or ...2-cell (2S) batteries. The proposed topology relocates the inductor from the high-current output to the low-current input, while providing step-down conversion ratios that take advantage of the higher voltage settings of Universal Serial Bus Type-C (USB-C) power delivery (PD). Moreover, moving the inductor to the input allows the parasitic inductance of a USB cable to be utilized in place of a discrete inductor, that is, a smart-cable architecture, eliminating the need for on-board magnetics and reducing on-board power dissipation. The converter is implemented in 7.37 mm 2 of a 130-nm BCD process and provides two outputs with ranges of 3-4.2 V and 6-8.4 V from a 9V input. With a 1μH discrete inductor, the prototype achieves peak powers of 12.2W and 31.9W and peak efficiencies of 94.3% and 97.4% for each output, respectively. The prototype is also demonstrated in a smart-cable architecture to limit on-board dissipation to 630 mW while delivering 7.2W at the first output or 350mW while delivering 14.4W at the second output. Simultaneous data and power transfer and electromagnetic interference (EMI) tests are provided to support the feasibility of integration into a smart-cable architecture.
Although switched-capacitor (SC) multilevel inverters (MLIs) offer self-voltage balancing of flying capacitors and voltage gain higher than unity, the advantages come at the cost of high current ...stress and power loss in the SC circuit and dc source. Moreover, the voltage balancing is often restricted to a limited range of modulation indices. Another problem of MLIs with neutral-point clamped (NPC) front end is with dc-link capacitor voltage balancing under unbalanced load conditions, imploring sensor-based closed-loop control. This article proposes a unity gain five-level active-NPC SC-MLI with inrush charging current attenuation and actively balanced dc-link capacitor voltages under all load conditions and over the entire range of modulation index and power factor. The modified pulsewidth modulation (PWM) results in most switches operating at a low switching frequency, minimizing switching losses in the SC circuit. The proposed MLI attains a maximum efficiency of 98.04% at an output power of 510 W. Experiments on a 2 kVA laboratory prototype validate the theoretical analysis. Results from transformerless grid-connected solar photovoltaic (PV) system show that the proposed MLI can inject power into the grid with a unity power factor under conditions of varying irradiance and provide the grid with reactive power as well.
Stochastic computing (SC) is a promising technique for applications that require low area overhead and fault tolerance, but can tolerate relatively high latency. In the SC paradigm, logical ...computation is performed on randomized bit streams. In prior work, streams were generated with linear feedback shift registers; these contributed heavily to the hardware cost and consumed a significant amount of power. This paper introduces a new approach for encoding signal values: computation is performed on analog periodic pulse signals. Exploiting pulse width modulation, time-encoded signals corresponding to specific values are generated by adjusting the frequency and duty cycles of pulse width modulated (PWM) signals. With this approach, the latency, area, and energy consumption are all greatly reduced. Experimental results on image processing applications show up to 99% performance speedup, 98% saving in energy dissipation, and 40% area reduction compared to prior stochastic approaches. Circuits synthesized with the proposed approach can work as fast and energy-efficiently as a conventional binary design while retaining the fault-tolerance and low-cost advantages of conventional stochastic designs.
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