The series-stacked architecture provides a method to increase power delivery efficiency to multiple processors by leveraging the inherent voltage step-down properties of series-connected elements. ...With a series stack, differential power processing (DPP) is needed to ensure that processor voltages remain within design limits, as the individual loads vary. This paper demonstrates a switched-capacitor (SC) converter to balance a stack of four ARM Cortex-A8-based embedded computers. We investigate hard-switched and resonant modes of operation in a ladder SC DPP converter implemented with GaN transistors. Operation within supply limits of each embedded computer is demonstrated in a four-series-stack configuration with realistic computational workloads. Moreover, we demonstrate hot-swapping of individual computers with maintained voltage regulation at all nodes. A peak stack power delivery of 99% is experimentally measured, and DPP switching frequencies from 200 kHz to 2 MHz are demonstrated.
The use of a switched capacitor (SC) dc-dc converter for tracking the maximum power point (MPP) of a photovoltaic (PV) array with the possibility of partial shading is described. The SC converter ...topology can be reconfigured to maximize conversion efficiency depending on the solar radiation and load. A new control scheme for MPP tracking based on tuning the input resistance (R _{\rm IN} ) of the SC converter MPP tracker with a battery tied load to match the output resistance of the array at MPP is proposed. R _{\rm IN} of the SC converter MPP tracker is studied extensively. The limits of R _{\rm IN} and its sensitivity to Pulse-width modulation (PWM), frequency modulation (FM), and circuit parameters of the SC converter are analyzed. Based on the sensitivity analysis, the proposed control scheme consists of an inner FM loop for fine control, an outer PWM loop for coarse control, and a provision to increase the dynamic range of R _{\rm IN} with adjustments of certain converter circuit parameters. A hardware prototype of a 10-W SC converter-based MPP tracker is built. Experimental measurements on the hardware model confirm the theoretical analysis. An algorithm to implement the MPP tracking control scheme is also tested.
This paper presents a hybrid-switched-capacitor-resonant (HSCR) light-emitting diode (LED) driver based on a stackable switched-capacitor (SC) converter IC rated for 15-20-W applications. Bulky ...transformers have been replaced with an SC ladder to perform high-efficiency voltage step-down conversion; an <inline-formula> <tex-math notation="LaTeX">LC </tex-math></inline-formula>-resonant output network provides almost lossless current regulation and demonstrates the potential of capacitive galvanic isolation. The integrated SC modules can be stacked in the voltage domain to handle a large range of input voltage ranges that largely exceed the voltage limitation of the medium-voltage-rated 120-V silicon technology. The LED driver demonstrates >91% efficiency over a rectified input dc voltage range from 160 to 180 V dc with two stacked ICs; using a stack of four ICs >89.6% efficiency is demonstrated over an input range from 320 to 360 V dc . The LED driver can dim its output power to around 10% of the rated power while maintaining >70% efficiency with a pulsewidth modulation-controlled clock gating circuit.
Motivated by emerging self-sustained low-power applications, an integrated power supply solution with a reconfigurable step-up/down switched-capacitor power stage and a dual-loop adaptive gain-pulse ...control is presented. It makes use of a reconfigurable power stage structure to implement variable gain ratios that provide efficient voltage conversion within wide input/output voltage and power ranges. It also employs an interleaving regulation scheme to significantly reduce the input inrush currents and the output voltage ripples with fast transient response. Design strategy, system optimization, and circuit implementation are addressed in detail. The converter was designed with a standard 0.35-mum digital CMOS n-well process. With an input voltage ranging from 1.5 to 3.3 V, the converter achieves variable step-up/down voltage conversion with a maximum load current of 90 mA. The maximum efficiency is 88%. The converter responds to a 70-mA load-current step change within 4.6 mus, while it robustly operates under a 1.8-V input supply variation. The design can be easily extended and reconfigured for different operation and application scenarios.
An Integrated 3-mW 120/230-V AC Mains Micropower Supply Lutz, Daniel; Renz, Peter; Wicht, Bernhard
IEEE journal of emerging and selected topics in power electronics,
2018-June, 2018-6-00, Letnik:
6, Številka:
2
Journal Article
Recenzirano
The maintenance issue of batteries and the limited power level of energy harvesting is addressed by the presented integrated micropower supply. Connected to the 120/230-<inline-formula> <tex-math ...notation="LaTeX">\text {V}_{\text {RMS}} </tex-math></inline-formula> mains, it provides a 3.3-V ac output voltage, suitable for applications such as the Internet-of-Things and smart homes. The micropower supply consists of a fully integrated ac-dc and dc-dc converter with one external low-voltage surface mount device buffer capacitor, resulting in an extremely compact size. Fabricated in a low-cost 0.35-<inline-formula> <tex-math notation="LaTeX">\mu \text {m}~700 </tex-math></inline-formula>-V complimentary metal-oxide-semiconductor technology, it covers a die size of 7.7 mm 2 . The ac-dc converter is a direct coupled, full-wave rectifier with a subsequent series regulator. The dc-dc stage is a fully integrated capacitive 4:1 converter with up to 17-V input and 47.4% peak efficiency. The power supply comprises several high-voltage control circuits including level shifters and various types of charge pumps (CPs). A source-supplied CP is utilized that supports a varying switching node potential. The overall losses are discussed and optimized, including flying capacitor bottom-plate losses. The power supply achieves an output power of 3 mW, resulting in a power density of 390 <inline-formula> <tex-math notation="LaTeX">\mu \text {W}/ \text {mm}^{2} </tex-math></inline-formula>. This exceeds prior art by a factor of 11.
This paper presents a fully passive 13.56 -MHz RFID temperature sensor system-on-chip. Its power management unit operates over a large temperature range using a zero temperature coefficient bias ...source. On-chip temperature sensing is accomplished with low-voltage, low-power CMOS circuitry, and time-domain signal processing. Two readout commands have been defined to study supply noise sensitivity: 1) standard readout, where just a single set of data is transferred to the reader and 2) serial readout, where several sets of data are sent one after the other to the reader. With the standard readout command, the sensor suffers from interference from the RFID command packet and outputs interference as well, while the sensor outputs no interference with the serial readout command. Measurements show that sensor resolution with serial readout is improved by a factor of approximately 16 compared to standard readout. The chip was fabricated in a standard 0.35-<inline-formula> <tex-math notation="LaTeX"> \mu \text{m} </tex-math></inline-formula> CMOS technology and chip-on-board mounted to a tuned RFID transponder coil on an aluminum core FR4 PCB substrate. Real-time wireless temperature sensing has been demonstrated with a commercial HF RFID reader. With a two-point calibration, the SoC achieves a <inline-formula> <tex-math notation="LaTeX">{3\sigma } </tex-math></inline-formula> sensing accuracy of ±0.4 °C from 0 °C to 125 °C.
This paper presents a low-area low-power Switched-Capacitor (SC)-based Programmable-Gain Analog-to-Digital Converter (PG-ADC) suitable for in-channel neural recording applications. The PG-ADC uses a ...novel implementation of the binary search algorithm that is complemented with adaptive biasing techniques for power saving. It has been fabricated in a standard CMOS 130 nm technology and only occupies 0.0326 mm 2 . The PG-ADC has been optimized to operate under two different sampling modes, 27 kS/s and 90 kS/s. The former is tailored for raw data conversion of neural activity, whereas the latter is used for the on-the-fly feature extraction of neural spikes. Experimental results show that, under a voltage supply of 1.2 V, the PG-ADC obtains an ENOB of 7.56 bit (8-bit output) for both sampling modes, regardless of the gain setting. The amplification gain can be programmed from 0 to 18 dB. The power consumption of the PG-ADC at 90 kS/s is 1.52 μW with a FoM of 89.49 fJ/conv, whereas at 27 kS/s it consumes 515 nW and obtains a FoM of 98.31 fJ/conv .
This paper introduces a practical power management integrated circuit (IC) building block, i.e., IC module, which enables the implementation of various emerging hybrid and multilevel power converter ...topologies in low-power high-frequency applications, operating at switching frequencies up to 10 MHz. Compared to conventional buck- and boost-based topologies, the emerging multilevel and hybrid converters offer significant volume reduction and power processing efficiency improvements. These key factors are significant contributions for modern portable and/or small footprint electronics devices, where size is of great concern. The IC building block (ICBB) consists of two segmented half bridges as well as all the elements needed for implementing mixed-signal current programmed mode (CPM) control. Mixed-signal CPM compatibility coupled with a segmented power stage not only provide inherent current protection and simple controller implementation but also allows for dynamic efficiency optimization. Operation at high-switching frequencies and simple modular design with ICBB are enabled through the development of novel architectures for key functional blocks of the ICBB and a cost-effective solution for level shifting, providing communication between external control signals and module inputs. For example, solutions for high-frequency low-power current sensing and fast digital-to-analog conversion are introduced as well as a capacitive coupling and coding schemes for data transfer. Several identical custom-designed ICBB modules are fabricated in the 0.13-<inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula> CMOS process, each providing up to 2 W of output power, while operating at a switching frequency of up to 10 MHz. The versatility and proper functionality of these modules are verified through simulation and experimental results.
This paper presents a generalized circuit structure of bi-directional switched-capacitor dc/dc converters that feature voltage step-down, voltage step-up, and bi-directional power flow. The starting ...point is the derivation of two structures of single-capacitor bi-directional converter cells. Current control scheme is applied in the capacitor-charging phase, resulting in a near-constant capacitor charging current and low electromagnetic interference. A converter string is then formulated by cascading a number of converter cells, in order to meet the input and output voltage requirements and conversion efficiency. By paralleling two similar strings and operating them in the anti phase, the overall converter input current becomes continuous. A reduced-order modeling and state-space averaging technique are used to study the static and dynamic behavior of the converter. The theoretical conversion efficiency in the step-down and step-up mode, respectively, is investigated for different voltage-conversion ratios and numbers of stages. The performance of the proposed structure is experimentally verified on a 5-V/12-V prototype.
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