A ground-isolated switched capacitor (SC) dc-dc converter-based current equalization scheme for partially shaded photovoltaic (PV) strings of a grid-connected system is presented. SC converters are ...compact, light, and have very high efficiency even for a wide variation in load under certain operating conditions. These features make them ideal for integration with the PV module for current equalization. The factors affecting the maximum output power that the SC converter can deliver, the limiting value of the maximum output power, and efficiency issues of the SC converter are studied. These studies are required to optimize the design of the equalizing SC converter and to maximize its efficiency. A novel algorithm that utilizes the results of the aforementioned analysis to maximize the net power available due to the SC converter-based current equalization scheme for grid-connected applications is proposed. Experimental results showing the advantages of current equalization with SC converters as compared to that with conventional dc-dc converters are presented.
A digital correction scheme that allows a switched-capacitor (SC) ΔΣ ADC to operate with significantly reduced power consumption is proposed. As power dissipation is reduced in the integrators, ...nonlinear settling errors cause increasing harmonic distortion. The correction technique uses a polynomial approximation to correct the nonlinearity and reduce distortion in the post-filtered digital output. With correction, experimental results yield a peak SNDR of 75 dB, a THD of -90 dB and a SFDR of 94 dB. The total analog power dissipation of the corrected modulator is 5 mW at 2.4 V, saving 38% over a similarly performing uncorrected modulator output. The active area is 0.39 mm 2 in 0.25-μ m CMOS.
In this brief, a low-power high-resolution readout front end intended for capacitive sensors is presented, in which the circuit uses correlated-level-shifting (CLS) and chopperstabilization (CS) ...techniques. CLS is a relatively new switchedcapacitor (SC) technique that is used to reduce errors from finite operational amplifier (op-amp) gain, whereas CS is a classic technique that is used to reduce the adverse effects of dc offset and low-frequency noise associated with the op-amp. In this brief, the capacitive sensor is physically emulated by a pair of on-chip differential variable capacitors that are in the femtofarad range. The proposed front end is designed in a 0.8-μm CMOS technology and consumes 290 μW from a single 5-V supply. The readout circuit achieves a capacitance noise floor of 0.018 aF/√Hz at 400 Hz with a sensitivity of 50 mV/fF.
We present modeling techniques for accurate estimation of settling errors in switched-capacitor (SC) circuits built with Miller-compensated operational transconductance amplifiers (OTAs). One ...distinctive feature of the proposal is the computation of the impact of signal levels (on both the model parameters and the model structure) as they change during transient evolution. This is achieved by using an event-driven behavioral approach that combines small- and large-signal behavioral descriptions and keeps track of the amplifier state after each clock phase. Also, SC circuits are modeled under closed-loop conditions to guarantee that the results remain close to those obtained by electrical simulation of the actual circuits. Based on these models, which can be regarded as intermediate between the more established small-signal approach and full-fledged simulations, design procedures for dimensioning SC building blocks are presented whose targets are system-level specifications (such as ENOB and SNDR) instead of OTA specifications. The proposed techniques allow to complete top-down model-based designs with 0.3-b accuracy.
Behavioral modeling of pipeline ADC building blocks Ruiz-Amaya, Jesús; Delgado-Restituto, Manuel; Rodríguez-Vázquez, Ángel
International journal of circuit theory and applications,
06/2012, Letnik:
40, Številka:
6
Journal Article
In recent years, inverter-based sigma-delta (ΔΣ) modulators have received great attention as a suitable approach for the design of low-voltage, low-power, switched-capacitor ΔΣ. This method uses ...digital inverters as the active elements to construct the integrators in the ΔΣ loop. In some applications, a reduced silicon area implementation is an important constraint; this demands the use of only one inverter in the integrator. This paper proposes to use the common-source amplifier as the building block to achieve the operation of integration instead of the digital inverter. This leads to the operation of the amplifier in strong inversion combined with low-voltage supply and compact chip area. The idea was confirmed with a prototype fabricated in a 0.5-μm CMOS technology available through Metal Oxide Semiconductor Implementation Service (MOSIS). Using 250 kHz of sampling frequency, measurement results show a signal-to-noise and distortion ratio of 70 dB over a bandwidth of 125 Hz. The circuit consumes 38 μW when powered from a single 1.5-V supply voltage and uses 200 × 260 μm of active area. Circuit simulations in SPICE show the potential of this method to work with 450 mV of power supply in a 50-nm CMOS technology.
Micropower gradient flow acoustic localizer Stanacevic, M.; Cauwenberghs, G.
IEEE transactions on circuits and systems. I, Regular papers,
10/2005, Letnik:
52, Številka:
10
Journal Article
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A micropower mixed-signal system-on-chip for three-dimensional localization of a broad-band acoustic source is presented. Direction cosines of the source are obtained by relating spatial and temporal ...differentials in the acoustic traveling wave field acquired across four coplanar microphones at subwavelength spacing. Correlated double sampling and least-squares adaptive cancellation of common-mode leakthrough in the switched-capacitor analog differentials boost localization accuracy at very low aperture. A second stage of mixed-signal least-squares adaptation directly produces digital estimates of the direction cosines. The 3mm /spl times/ 3mm chip in 0.5-/spl mu/m CMOS technology quantizes signal delays with 250-ns resolution at 16-kHz sampling rate, and dissipates 54 /spl mu/W power from a 3-V supply. Field tests of the processor with acoustic enclosure demonstrated its utility and endurance in tracking ground and airborne vehicles. Applications include acoustic surveillance, interactive multimedia, and intelligent hearing aids.
A 2.5-GHz phase-locked loop (PLL) employing a low-power active switched-capacitor loop filter is presented. A subthreshold inverter-based active loop filter is presented and analyzed. Advantages such ...as type-II loop dynamics, low reference spurs, and small on-chip capacitors are achieved. In addition, 1/f noise of the inverter amplifier can be suppressed by the filter's auto-zeroing operation. The prototype is designed and fabricated in a 0.18- μm CMOS technology. Measurement results show phase noise of -86 dBc/Hz at a 100-kHz offset, -124.0 dBc/Hz at a 3-MHz offset, and a reference spur level of -64 dBc. The PLL consumes about 16 mW with 0.46 mW dedicated to the loop filter active components.
This paper presents a new fully integrated sensing interface and signal-conditioning application-specific integrated circuit (ASIC) for automotive accelerometers based on an ldquoinjection-nulling ...switchrdquo (INS) technique. The INS technique simplifies the design of both the switched-capacitor (SC) sensing amplifier and its supporting building blocks without jeopardizing its performance. This is done by counteracting the impact of charge injection and clock-feedthrough effects on sensitivity, resolution, and offset. It also decreases the number of opamps, capacitors, and switches being used. This results in reduction of power consumption, potential switching noise, and noise (sampled thermal noise which increases with the number of SC pairs being used) in the ASIC. A two-chip approach has been adopted in the implementation, with sensing element and ASIC. The built-in trimming circuitry and signal-conditioning blocks, which includes a self-test circuit, are implemented internally to eliminate the need for external components. The experimental results have shown that the sensing system IC has achieved a power consumption of 10 mW (2 mA at 5 V), a maximum noise root spectral density of 11.87 equivalent to rms noise root spectral density of 0.187 at 15.63 Hz, a signal-to-noise dynamic range of 77dB for 500-Hz bandwidth and 74 dB for 1-kHz bandwidth based on 50 g, and a maximum clock noise of 1.562 mV. The die size of the ASIC is 2.8 mm 2.3 mm using a standard 0.6- mum CMOS technology.
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