This paper presents a 35 GHz differential variable gain amplifier (VGA) with 4‐bit digital‐controlled gain‐tuning using 65‐nm CMOS process. Using the proposed miniaturized differential matching ...inductors, a core size of the VGA is only 0.53 × 0.26 mm. The digital gain control mechanism is achieved using the digital version current steering topology. The measured gain control range of the VGA is from 17.4 to 9 dB at 35 GHz with 16 different linear‐in‐dB gain states. Thus, this work achieves the maximum peak gain per unit core size and maintains a much better gain control range per unit core size. The measured root mean square gain error is <0.29 dB and phase error is < 4.6° from 34 to 36.5 GHz.
In Bresenham's line drawing algorithm, the points of an n-dimensional raster that have to be selected are determined forming a close approximation to a straight line existed between two points. It is ...widely used for drawing line primitives in a bitmap image (for example: on a computer screen), since only integer addition, subtraction and bit shifting are used. These three operations are cheap concerning standard computer architectures. In addition, it is an incremental error algorithm. It is among the oldest algorithms that have been developed in computer graphics. An extension to the original algorithm may lead to draw circles. This research deals with the Bresenham’s line and circle drawing algorithm based on FPGA hardware platform. The shapes on the VGA screen are displayed via internal VGA port that is built in the device.
Analyzing time series from the perspective of complex network has interested many scientists. In this paper, based on visibility graph theory a novel method of constructing weighted complex network ...from time series is proposed. The first step is to determine the weights of vertices in time series, which linearly combines the weights generated by induced ordered averaging aggregation operator (IOWA) and visibility graph aggregation operator (VGA). Then, two strategies, averaging strategy and gravity strategy, are proposed to construct weighted network. To testify the validity of proposed method, an artificial case is adopted, in which link prediction is used to evaluate the performance of the weighted network. It is shown that the weighted network constructed by proposed method greatly outperforms the unweighted network obtained by traditional visibility graph theory.
Livestock-associated methicillin-resistant
(LA-MRSA) isolates of the clonal complex 398 are often resistant to a number of antimicrobial agents. Studies on the genetic basis of antimicrobial ...resistance in these bacteria identified SCC
cassettes, various transposons and plasmids of different sizes that harbor antimicrobial resistance genes. While large plasmids that carry multiple antimicrobial resistance genes - occasionally together with heavy metal resistance genes and/or virulence genes - are frequently seen in LA-MRSA ST398, certain resistance genes are also associated with small plasmids of up to 15 kb in size. These small resistance plasmids usually carry only one, but in rare cases also two or three antimicrobial resistance genes. In the current review, we focus on small plasmids that carry the macrolide-lincosamide-streptogramin B resistance genes
(C) or
(T), the lincosamide resistance gene
(A), the pleuromutilin-lincosamide-streptogramin A resistance genes
(A) or
(C), the spectinomycin resistance gene
, the apramycin resistance gene
, or the trimethoprim resistance gene
. The detailed analysis of the structure of these plasmids allows comparisons with similar plasmids found in other staphylococci and underlines in many cases an exchange of such plasmids between LA-MRSA ST398 and other staphylococci including also coagulase-negative staphylococci.
A patient with a history of UTI acquired an isolate of Staphylococcus saprophyticus that was resistant to clindamycin, streptogramin A, pleuromutilins (LSPs), and oxacillin. A plasmid-located vga ...variant was identified in this pathogen, and the encoded protein showed a 39% to 67% identity to other previously characterized vga.
We report the design and analysis of a 28 GHz CMOS low-noise amplifier (LNA) and variable-gain amplifier (VGA1) using coupled-transmission-line (CTL)-feedback technique, and another VGA (VGA2) ...without CTL-feedback for contrast. The CTL in conjunction with a coupling capacitance (<inline-formula> <tex-math notation="LaTeX">C_{\text{ctl}})</tex-math> </inline-formula> contributes an in-phase gain at the output of the input stage. Over 21.9-29.1 GHz, 0.6-2.4 dB boosting in <inline-formula> <tex-math notation="LaTeX">S_{\text{21}}</tex-math> </inline-formula> and 0.42-1.17 dB reduction in noise figure (NF) are achieved. The body-floating technique is used for NF reduction due to effective suppression of the substrate noise. An auxiliary-gain-linearity-enhancement (AGLE) stage is included in parallel with the output stage for gain and linearity boosting since it contributes an in-phase gain and exhibits better linearity due to higher drain-source voltage (<inline-formula> <tex-math notation="LaTeX">V_{\text{DS}})</tex-math> </inline-formula>. For VGA1 and VGA2, an analog current-steering switch transistor <inline-formula> <tex-math notation="LaTeX">M_{\text{5}}</tex-math> </inline-formula> is in parallel with the output stage to tune its overdrive and <inline-formula> <tex-math notation="LaTeX">V_{\text{DS}}</tex-math> </inline-formula> for fine tuning of <inline-formula> <tex-math notation="LaTeX">S_{\text{21}}</tex-math> </inline-formula>. Digital switch transistor <inline-formula> <tex-math notation="LaTeX">M_{\text{6}}</tex-math> </inline-formula> (in conjunction with the coupling capacitance <inline-formula> <tex-math notation="LaTeX">C_{\text{3}}</tex-math> </inline-formula> and resonant inductance <inline-formula> <tex-math notation="LaTeX">L_{\text{res}})</tex-math> </inline-formula> is in parallel with the gain stage to control its ac <inline-formula> <tex-math notation="LaTeX">V_{\text{DS}}</tex-math> </inline-formula> for coarse tuning of <inline-formula> <tex-math notation="LaTeX">S_{\text{21}}</tex-math> </inline-formula>. VGA1 adopts DTMOS-with-<inline-formula> <tex-math notation="LaTeX">R_{B}</tex-math> </inline-formula> switch for lower on-state (<inline-formula> <tex-math notation="LaTeX">R_{\text{ch,on}})</tex-math> </inline-formula> and higher off-state channel resistance (<inline-formula> <tex-math notation="LaTeX">R_{\text{ch,off}})</tex-math> </inline-formula>. This leads to <inline-formula> <tex-math notation="LaTeX">S_{\text{21}}</tex-math> </inline-formula> tuning range boosting. The LNA consumes 9.5 mW and achieves <inline-formula> <tex-math notation="LaTeX">S_{\text{21}}</tex-math> </inline-formula> of 21.8 <inline-formula> <tex-math notation="LaTeX">\pm</tex-math> </inline-formula> 1.5 dB for 21.9-29.1 GHz (<inline-formula> <tex-math notation="LaTeX">f_{\text{3\,dB}}</tex-math> </inline-formula> <inline-formula> <tex-math notation="LaTeX">=</tex-math> </inline-formula> 7.2 GHz), minimum NF (NF<inline-formula> <tex-math notation="LaTeX">_{\text{min}})</tex-math> </inline-formula> of 1.98 dB, and average NF (NF<inline-formula> <tex-math notation="LaTeX">_{\text{avg}})</tex-math> </inline-formula> of 2.32 dB, and figure-of-merit (FOM<inline-formula> <tex-math notation="LaTeX">_{\text{2}})</tex-math> </inline-formula> of 74.1 nm<inline-formula> <tex-math notation="LaTeX">\cdot </tex-math> </inline-formula>GHz<inline-formula> <tex-math notation="LaTeX">^{\text{2/3}}</tex-math> </inline-formula>/mW<inline-formula> <tex-math notation="LaTeX">^{\text{1/3}}</tex-math> </inline-formula>. VGA1 consumes 13.2 mW and achieves <inline-formula> <tex-math notation="LaTeX">S_{\text{21}}</tex-math> </inline-formula> of 20.1 <inline-formula> <tex-math notation="LaTeX">\pm</tex-math> </inline-formula> 1.5 dB for 20.5-27.6 GHz (<inline-formula> <tex-math notation="LaTeX">f_{\text{3\,dB}}</tex-math> </inline-formula> <inline-formula> <tex-math notation="LaTeX">=</tex-math> </inline-formula> 7.1 GHz), <inline-formula> <tex-math notation="LaTeX">S_{\text{21}}</tex-math> </inline-formula> tuning range of 36.8 dB, NF<inline-formula> <tex-math notation="LaTeX">_{\text{min}}</tex-math> </inline-formula> of 1.74 dB, NF<inline-formula> <tex-math notation="LaTeX">_{\text{avg}}</tex-math> </inline-formula> of 2.1 dB, and FOM<inline-formula> <tex-math notation="LaTeX">_{\text{2}}</tex-math> </inline-formula> of 66.5 nm<inline-formula> <tex-math notation="LaTeX">\cdot </tex-math> </inline-formula>GHz<inline-formula> <tex-math notation="LaTeX">^{\text{2/3}}</tex-math> </inline-formula>/mW<inline-formula> <tex-math notation="LaTeX">^{\text{1/3}}</tex-math> </inline-formula>. The NF<inline-formula> <tex-math notation="LaTeX">_{\text{avg}}</tex-math> </inline-formula> and FOM<inline-formula> <tex-math notation="LaTeX">_{\text{2}}</tex-math> </inline-formula> are one of the best results ever reported for LNAs and VGAs with <inline-formula> <tex-math notation="LaTeX">f_{\text{3\,dB}}</tex-math> </inline-formula> greater than 5 GHz and power dissipation lower than 15 mW.
This article presents a 17.720.2 GHz eight-element four-beam RF-beamforming transmitter in 65-nm CMOS for satellite communication (SATCOM). The transmitter utilizes an analog scheme in the ...variable-gain amplifier (VGA) to achieve dB-in-linear gain control with a high dynamic range (DR), together with a current combining crossbar for a compact footprint. The vector-modulation-based (VM-based) phase shifter (PS) adopts the cancellation-based <inline-formula> <tex-math notation="LaTeX">G_\mathrm{m}</tex-math> </inline-formula> units for low switching variation. Furthermore, eight PSs of each beam are split into two groups, with each group sharing the same tunable I/Q generator for low power consumption. Considering the increased peak-to-average power ratio (PAPR) caused by high-order modulation schemes and multibeam operation, the transmitter incorporates compact transformer-based Doherty power amplifiers (DPAs) with adaptive bias control to improve the power efficiency at back-off. The chip achieves a 31-dB gain-tuning range with a 0.283-dB step and a 360<inline-formula> <tex-math notation="LaTeX">^{\circ}</tex-math> </inline-formula> phase-shifting range with a calibrated 7-bit resolution. The measured root-mean-square (RMS) phase/gain errors induced by the VGA/PS are below 2.05<inline-formula> <tex-math notation="LaTeX">^{\circ}</tex-math> </inline-formula>/0.147 dB, respectively, which decouples phase/gain control. The transmitter achieves a maximum output 1-dB gain compression point (OP<inline-formula> <tex-math notation="LaTeX">_{\mathrm{1 dB}}</tex-math> </inline-formula>) of 17.9 dBm and a maximum saturated power (<inline-formula> <tex-math notation="LaTeX">P_{\mathrm{sat}}</tex-math> </inline-formula>) of 18.9 dBm. The output element exhibits 29.3% drain efficiency (DE) at 6-dB power back off (PBO) from <inline-formula> <tex-math notation="LaTeX">P_{\mathrm{sat}}</tex-math> </inline-formula>, which is 1.56/3.12 times over the normalized class-B/class-A implementations, demonstrating Doherty PBO efficiency enhancement. The chip occupies an area of 8.59 <inline-formula> <tex-math notation="LaTeX">\times</tex-math> </inline-formula> 4.17 mm<inline-formula> <tex-math notation="LaTeX">^2</tex-math> </inline-formula> and consumes 398 mW per element at OP<inline-formula> <tex-math notation="LaTeX">_{\mathrm{1~dB}}</tex-math> </inline-formula>. Additionally, a 16-element linear array has been developed to showcase the capabilities of the multibeam operation and gain tapering.
In this article, we present a detailed analysis of current steering, wideband, low noise, variable gain amplifier (VGA) and a novel method to decrease its phase and amplitude errors. A low noise VGA ...(LNVGA) has been designed using this innovative method in IHP's 0.13 <inline-formula> <tex-math notation="LaTeX">\mu</tex-math> </inline-formula>m SiGe BiCMOS technology. In this proposed method, a high impedance seen from the base of the current steering transistor replaces a low impedance to reduce the loading of the current steering device and phase variations, eventually. The operating frequency spans from 8 to 18 GHz. The measurements indicate that the maximum gain is 12.4 dB, and the minimum noise figure (NF) is 1.93 dB at the reference state. The minimum measured root-mean-square (rms) phase and amplitude errors are 0.8<inline-formula> <tex-math notation="LaTeX">^{\circ}</tex-math> </inline-formula> and 0.04 dB, respectively, for a 0.5 dB step size and 16 dB attenuation range. The attenuation range can be increased by up to 30 dB, albeit at the cost of accruing additional phase and amplitude errors. The dc power consumption of the design is 24 mW, and the maximum input 1-dB compression point is 3.9 dBm. The overall dimensions of the chip is 0.58 mm<inline-formula> <tex-math notation="LaTeX">^2</tex-math> </inline-formula> including pads.
This paper presents a 28-GHz common-leg phased-array front-end in 45-nm CMOS silicon on insulator with transmit and receive capabilities. The design alternates cascode amplifiers with passive ...switched-<inline-formula> <tex-math notation="LaTeX">LC </tex-math></inline-formula> phase-shifter cells to result in 5-bit phase control with an rms phase and gain error <4° and <0.8 dB, respectively, at 24-30 GHz, over 32 phase states. The front-end has 2- and 3-bit variable gain amplifiers with 7.5-dB total gain control, without affecting the system noise figure (NF). Two low-loss high-linearity single-pole double-throw switches are used to switch between transmit and receive modes. In the receive (Rx) mode, the measured gain, NF, input 1-dB compression point (P 1dB ), and input third-order intercept point are 16 dB, 3.7 dB, −15 dBm, and −7 dBm, respectively, with 54-mW dc power consumption. In the transmit (Tx) mode, measurements show 16.5-dB gain, an output P 1dB of 8 dBm, and an output IP3 of 16 dBm with 100-mW dc power consumption. The error-vector magnitude and adjacent-channel-power-ratio measurements demonstrate quadrature phase-shift keying, 16-quadrature amplitude modulation (QAM), 64-QAM, and 16-QAM orthogonal frequency-division multiplexing modulations with several symbol-rates reaching up to 8 Gb/s data-rate for both the Rx and Tx modes at 2- and 5-dB back-off. The application areas are in fifth-generation phased arrays requiring high-linearity receivers and using external front-end modules for added transmit power.
An active, compact, wideband, receiving filtenna with power adaptation for space-limited wireless platforms is presented. By organically combining a filtering antenna and a Variable Gain Amplifier ...(VGA), the proposed co-designed active filtenna is achieved. Its power adaptation is empowered by controlling gain of the VGA unit. A demonstrated prototype with a compact overall size is fabricated, assembled and measured. Good performances are achieved. Furthermore, in any condition, the proposed active filtenna displays outstanding impedance matching (|S11| < −10 dB) and high passband skirt selectivity at upper and lower stopbands (Selectivity ≥ 170 dB/GHz).
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