This article presents a generator of digital modulations in FPGA for the teaching and the practice in Telecommunication laboratory. With the increasing demand for technological tools to be used in ...practical classes, this generator is an alternative to the use of commercial measurement equipments, it presents great flexibility, but at a high cost; and also, to the use of specific laboratory kits, which have a lower cost but have little flexibility. The design, its implementation and tests are showed in this work. Finally, the results are compared to a commercial kit, showing the viability of using this project for laboratory practice.
Fractional-<inline-formula> <tex-math notation="LaTeX">N </tex-math></inline-formula> frequency synthesizers that use a digital <inline-formula> <tex-math notation="LaTeX">\Delta ...</tex-math></inline-formula>-<inline-formula> <tex-math notation="LaTeX">\Sigma </tex-math></inline-formula> modulator (DDSM) to control the feedback divider can exhibit spurious tones that move about in the frequency domain; these are known colloquially as "walking" or wandering spurs. Building upon a theoretical explanation of the origin of wandering spurs, this article presents two methods to suppress them. It describes a 4.9-GHz 180-nm SiGe BiCMOS charge-pump phase-locked loop (CP-PLL) fractional-<inline-formula> <tex-math notation="LaTeX">N </tex-math></inline-formula> frequency synthesizer platform with a divider controller that can function as: 1) a standard MASH 1-1-1; 2) a MASH 1-1-1 with high-amplitude dither; and 3) a MASH 1-1-1 with a modified third stage. Measurements confirm the effectiveness of the wandering spur suppression strategies.
This article discusses modern techniques of implementation of a wideband digital modulator in an FPGA kit for use in electrical engineering communications laboratory. Previous configurations proposed ...in literature present limitations, as lack of details about the methods used in the algorithm developed and test procedures. Those key details can help researchers to develop this modulator more effectively. From technical point of view, previous works were also implemented for small bandwidth output signals. The proposed digital modulator has low cost and can generate signals based on several modulation schemes with various output roll-off filters. This proposed kit allows researchers to change digital signal characteristics through dip-switches, customizing the modulated signal. Advanced techniques such as parallelism of processes and fast access to look up tables using an FPGA were used to achieve the desired objective, and are detailed in the article. Besides this implementation, this article also shows test procedures to validate the performance of digital modulators using lab test equipment. Those procedures were used to validate the FPGA modulator developed. The paper shows how researchers can analyze the performance of digitally modulated output signals using an Oscilloscope, a Spectrum Analyzer, and a Vector Signal Analyzer. Features such as symbol rate, modulation constellation, roll-off output filter, and EVM are covered.
One of the prerequisites of electronic warfare (EW) is to have the means to provide secure point-to-point wireless data and voice communications with other ground stations. New technologies are ...giving rise to bigger information security threats. This situation illustrates the best the urgency of reducing the development time of EW systems. Previous works suggest that digital systems are the best candidates for this purpose and therefore form the backbone of modern EW. As a result, digital modulation techniques are widely used in modern wireless communication systems. This is largely due to their high resistance to noise and their high transmission capacity that can be achieved through data multiplexing. In this Letter, a new reconfigurable architecture of a phase shift keying (PSK) modulator is described and implemented on FPGA. The latter can be configured in real time to produce the following modulation schemes: QPSK, 8-PSK, and 16-PSK without having to regenerate the FPGA configuration bits. This action can be done by software via programming or manually using a DIP switch. The proposed design is implemented on the Xilinx xc7k325tfbg900 FPGA using the Genesis 2 development board. The experimental results are in agreement with the simulations.
FPGA Realisation of n-QAM Digital Modulators Galaviz-Aguilar, J. A.; Nuñez-Perez, J. C.; Perez-Pinal, F. J. ...
Technical review - IETE,
20/5/4/, Letnik:
36, Številka:
3
Journal Article
Recenzirano
This article introduces a novel modulators' design approach by applying direct digital generation capabilities that improve the development, synthesis, and verification of wireless transmitter ...systems. In this manner, digital modulators' that are able to process 8-, 16-, and 64-quadrature amplitude, are realised herein by using embedded systems like the well-known field-programmable gate array (FPGA). It is worth mentioning that using FPGAs allows us to perform a reduction of the hardware resources. This issue also allows relaxing the operating conditions of the systems in the digital domain. Several experiments are shown to demonstrate the usefulness of an FPGA, like using Stratix III DSP Development Kit, and to confirm the good agreement of the experimental results with theoretical ones.
Digital linear GFSK demodulator for IoT devices Aldana-Lopez, Rodrigo; Valencia-Velasco, Jose; Longoria-Gandara, Omar ...
IET communications,
10/2018, Letnik:
12, Številka:
16
Journal Article
Recenzirano
Companies and developers of emerging Internet-of-Things (IoT) technologies consider Bluetooth low-energy (BLE) standard as a strong candidate to be the backbone of wireless IoT devices and support ...their low-power requirements. Likewise, the BLE has adopted Gaussian frequency shift-keying (GFSK) signalling due to its power and spectral efficiencies, which are the most fundamental performance criteria for modulation schemes. For this reason, it is worthwhile to research and develop transceivers that maintain these advantages and achieve a low-complexity implementation for the digital modulator and demodulator. Different techniques have been proposed for this purpose, such as hardware usage optimisation, efficient pulse shaping and decomposition of the signal. This study presents a novel linear GFSK demodulator which has the following attractive advantages: low complexity, near-optimal performance in the additive white Gaussian noise channel and the possibility of operating with different GFSK modulators (with a nominal modulation index of 0.5) so it could be applied in BLE devices. In addition, the theoretical error probability is obtained and compared with simulation results.
Energy consumption is always a key feature in devices powered by electric accumulators. The power amplifier is the most energy-demanding module in mobile devices, portable appliances, static ...transceivers, and even nodes used in underwater acoustic networks. These devices incorporate a modulator, typically a pulse-width modulation (PWM) and a class-D power amplifier, for higher efficiency. We propose a technique to integrate the modulator of a transmitter and PW-modulator of a class-D amplifier to improve the overall efficiency of the system. This integrated set operates as an up-converter, phase modulator (PM), and binary phase-shift keying (BPSK) modulator under certain conditions. The theoretical concept is verified using Matlab and a model is designed and simulated in Simulink. For validation purposes, an electronic circuit is built and tested using Multisim. The results obtained by simulations and circuit implementation show that the proposed integrated system is an energy-efficient and cost-effective solution compared to conventional techniques.
Time-interleaved delta-sigma (ΔΣ) modulation digital-to-analog converters (TIDSM DACs) have the potential for a wideband operation. The performance of a two-channel interleaved ΔΣ DAC is very ...sensitive to the duty cycle of the half-rate clock. This brief presents a closed-form expression for the signal-to-noise-plus-distortion ratio (SNDR) loss of such DACs due to a duty-cycle error for modulators with a noise transfer function of (1 - z -1 ) n . Adding a low-order finite-impulse-response filter after the modulator helps to mitigate this problem. A closed-form expression for the SNDR loss in the presence of this filter is also developed. These expressions are useful for choosing a suitable modulator and filter order for an interleaved ΔΣ DAC in the early stage of the design process.
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