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Ki-Tae Park; Sangwan Nam; Daehan Kim; Pansuk Kwak; Doosub Lee; Yoon-He Choi; Myung-Hoon Choi; Dong-Hun Kwak; Doo-Hyun Kim; Min-Su Kim; Hyun-Wook Park; Sang-Won Shim; Kyung-Min Kang; Sang-Won Park; Kangbin Lee; Hyun-Jun Yoon; Kuihan Ko; Shim, Dong-Kyo; Ahn, Yang-Lo; Ryu, Jinho; Kim, Donghyun; Yun, Kyunghwa; Kwon, Joonsoo; Shin, Seunghoon; Byeon, Dae-Seok; Choi, Kihwan; Han, Jin-Man; Kyung, Kye-Hyun; Choi, Jeong-Hyuk; Kim, Kinam
IEEE journal of solid-state circuits, 01/2015, Letnik: 50, Številka: 1Journal Article
In this work, we present a true 3D 128 Gb 2 bit/cell vertical-NAND (V-NAND) Flash product for the first time. The use of barrier-engineered materials and gate all-around structure in the 3D V-NAND cell exhibits advantages over 1 × nm planar NAND, such as small Vth shift due to small cell coupling and narrow natural Vth distribution. Also, a negative counter-pulse scheme realizes a tightly programmed cell distribution. In order to reduce the effect of a large WL coupling, a glitch-canceling discharge scheme and a pre-offset control scheme is implemented. Furthermore, an external high-voltage supply scheme along with the proper protection scheme for a high-voltage failure is used to achieve low power consumption. The chip accomplishes 50 MB/s write throughput with 3 K endurance for typical embedded applications. Also, extended endurance of 35 K is achieved with 36 MB/s of write throughput for data center and enterprise SSD applications.
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Dostop do baze podatkov JCR je dovoljen samo uporabnikom iz Slovenije. Vaš trenutni IP-naslov ni na seznamu dovoljenih za dostop, zato je potrebna avtentikacija z ustreznim računom AAI.
Leto | Faktor vpliva | Izdaja | Kategorija | Razvrstitev | ||||
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JCR | SNIP | JCR | SNIP | JCR | SNIP | JCR | SNIP |
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Povezave do osebnih bibliografij avtorjev | Povezave do podatkov o raziskovalcih v sistemu SICRIS |
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Vir: Osebne bibliografije
in: SICRIS
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