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Ciobanu, M.; Herrmann, N.; Hildenbrand, K. D.; Kis, M.; Schuttauf, A.; Flemming, H.; Deppe, H.; Lochner, S.; Fruhauf, J.; Deppner, I.; Loizeau, P. A.; Trager, M.
IEEE transactions on nuclear science, 04/2014, Letnik: 61, Številka: 2Journal Article
The design of a general-purpose PreAmplifier-DIscriminator ASIC chip, PADI, is presented in this article. PADI is intended to be used as Front-End-Electronics (FEE) for reading out the timing Resistive-Plate Chambers (RPCs) in the time-of-flight (ToF) wall of the CBM detector for the future FAIR facility in Darmstadt-Germany, which will comprise about 100,000 channels in a 150 m 2 area. The evolution of this 0.18 μm CMOS technology design will be presented, from the first prototype PADI-1 to the last one, PADI-8, as well as its features and test results.
