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Chiu, Yen-Cheng; Zhang, Zhixiao; Chen, Jia-Jing; Si, Xin; Liu, Ruhui; Tu, Yung-Ning; Su, Jian-Wei; Huang, Wei-Hsing; Wang, Jing-Hong; Wei, Wei-Chen; Hung, Je-Min; Sheu, Shyh-Shyuan; Li, Sih-Han; Wu, Chih-I; Liu, Ren-Shuo; Hsieh, Chih-Cheng; Tang, Kea-Tiong; Chang, Meng-Fan
IEEE journal of solid-state circuits, 10/2020, Letnik: 55, Številka: 10Journal Article
Previous SRAM-based computing-in-memory (SRAM-CIM) macros suffer small read margins for high-precision operations, large cell array area overhead, and limited compatibility with many input and weight configurations. This work presents a 1-to-8-bit configurable SRAM CIM unit-macro using: 1) a hybrid structure combining 6T-SRAM based in-memory binary product-sum (PS) operations with digital near-memory-computing multibit PS accumulation to increase read accuracy and reduce area overhead; 2) column-based place-value-grouped weight mapping and a serial-bit input (SBIN) mapping scheme to facilitate reconfiguration and increase array efficiency under various input and weight configurations; 3) a self-reference multilevel reader (SRMLR) to reduce read-out energy and achieve a sensing margin 2<inline-formula> <tex-math notation="LaTeX">\times </tex-math></inline-formula> that of the mid-point reference scheme; and 4) an input-aware bitline voltage compensation scheme to ensure successful read operations across various input-weight patterns. A 4-Kb configurable 6T-SRAM CIM unit-macro was fabricated using a 55-nm CMOS process with foundry 6T-SRAM cells. The resulting macro achieved access times of 3.5 ns per cycle (pipeline) and energy efficiency of 0.6-40.2 TOPS/W under binary to 8-b input/8-b weight precision.
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JCR | SNIP | JCR | SNIP | JCR | SNIP | JCR | SNIP |
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in: SICRIS
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