The performance of n-type silicon nanosheets, nanowires, and FinFETs is benchmarked by Monte Carlo (MC) device simulation. Measurements of nanowire transfer characteristics are provided to validate the MC model supplemented by a corresponding comparison for nanosheets with literature data. At an OFF-current per effective gate width of 10 nA/<inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math> </inline-formula>, the ON-currents of nanowires, FinFETs, and nanosheets are 500, 545, and 570 <inline-formula> <tex-math notation="LaTeX">\mu \text{A}/\mu \text{m} </tex-math> </inline-formula>, respectively. A major reason for this inferior nanowire performance is found to be the stronger impact of surface roughness scattering in nanowires due to a higher surface-to-volume ratio. However, the nanowires’ performance disadvantage is reduced for shorter gate lengths due to their better electrostatic control and reduced impact of surface roughness upon scaling.