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Srinivasa, Srivatsa; Tu, Yung-Ning; Si, Xin; Xue, Cheng-Xin; Lee, Chun-Ying; Hsueh, Fu-Kuo; Shen, Chane-Hone; Shieh, Jia-Min; Yeh, Wen-Kuan; Ramanathan, Akshay Krishna; Ho, Mon-Shu; Sampson, Jack; Chang, Meng-Fan; Narayanan, Vijaykrishnan
2019 Symposium on VLSI Technology, 2019-JuneConference Proceeding
This paper presents the first monolithic 3D two-layer reconfigurable SRAM macro capable of executing multiple Compute-in-Memory (CiM) tasks as part of data readout. Fabricated using low cost FinFET based 3D+-IC, the SRAM offers concurrent data read from both layers and write from layer 2 with 0.4V \text{V}_{\text{dd}\min} 12.8x improved computation latency is achieved as compared to near memory computation of successive Boolean operations.
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| Leto | Faktor vpliva | Izdaja | Kategorija | Razvrstitev | ||||
|---|---|---|---|---|---|---|---|---|
| JCR | SNIP | JCR | SNIP | JCR | SNIP | JCR | SNIP | |
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| Povezave do osebnih bibliografij avtorjev | Povezave do podatkov o raziskovalcih v sistemu SICRIS |
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Vir: Osebne bibliografije
in: SICRIS
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