This article presents a compact <inline-formula> <tex-math notation="LaTeX">2\times </tex-math></inline-formula> time-interleaved switched-capacitor (SC) digital-to-analog converter (DAC) for digital-intensive transmitter architectures. To minimize area and to leverage the strengths of FinFET technology, the implementation departs from the traditional current steering approach and consists mainly of inverters and sub-femtofarad SCs. The DAC's architecture is based on parallel charge redistribution and separates level generation, pulse timing, and output power generation. The described 28-GS/s 8-bit prototype design occupies 0.03 mm 2 in 16-nm CMOS and supports up to 0.32-<inline-formula> <tex-math notation="LaTeX">\textrm {V}_{\textrm {pp}} </tex-math></inline-formula> signal swing across its differential 100-<inline-formula> <tex-math notation="LaTeX">{\Omega } </tex-math></inline-formula> load. It achieves an SFDR <inline-formula> <tex-math notation="LaTeX">\geq 37 </tex-math></inline-formula> dB and an IM<inline-formula> <tex-math notation="LaTeX">3\leq -45.6 </tex-math></inline-formula> dBc across the first Nyquist zone while consuming 88 mW from a single 0.8-V supply.