This paper presents an analysis of junction leakage in heavily doped p+/n germanium junctions, targeted for short-channel transistor fabrication. There exists an optimal p+/n junction condition, with a doping concentration of 1 times 10 17 -5 times 10 17 cm -3 , where the area-leakage-current density is minimal. Use of a halo-implant condition optimized for our 125-nm gate-length pMOS devices shows less than one decade higher area leakage than the optimal p+/n junction. For even higher doping levels, the leakage density increases strongly. Therefore, careful optimization of p+/n junctions is needed for decananometer germanium transistors. The junction leakage shows good agreement with electrical simulations, although for some implant conditions, more adequate implant models are required. Finally, it is shown that the area-junction static-power consumption for the best junctions remains below the power-density specifications for high-performance applications.