With high reliability and good cost-performance ratio, Si SJMOS and SiC SBD pair is often preferred in commercial single-phase PFC applications. Switching dynamics of Si SJMOS is different compared to 650<inline-formula><tex-math notation="LaTeX">\,</tex-math></inline-formula>V wide bandgap devices due to differences in device characteristics. This paper presents an improved analytical model to study the switching dynamics of Si SJMOS and SiC SBD pair. Unlike the existing literature on high-voltage Si MOSFETs, this paper considers the nonlinearities in channel current and internal capacitances of Si SJMOS, the nonlinear reverse-biased capacitance of SiC SBD, along with parasitic gate-drain capacitance arising due to PCB layout. As a result, the proposed analytical model presents a significant improvement over the existing models of high-voltage Si MOSFET in predicting switching loss, time, <inline-formula><tex-math notation="LaTeX">(dv/dt</tex-math></inline-formula>), <inline-formula><tex-math notation="LaTeX">(di/dt)</tex-math></inline-formula>, etc. Experimental and simulation results for three 650V Si SJMOS and SiC SBD pairs with different current ratings provide validation of the proposed analytical model.