Self-checking designs will gain increasing interest in industrial applications if they satisfy the following requirements: high fault coverage and reduced hardware cost with reduced design effort. The aim of this work is to contribute to reach these requirements for the design of self-checking adders/ALUs. In this paper, we present efficient self-checking XOR implementation for schemes using the dual duplication code. Among the known self-checking adder designs, the dual duplicated scheme has the advantage to be totally self-checking for single faults. The drawback of this scheme is that it requires generally the maximum hardware overhead. In this work, we propose a low cost self-checking implementation. The proposed design is a novel differential XOR gate implemented in CMOS pass transistor logic, and performed with only four transistors.