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Van den bosch, G.; Kar, G. S.; Blomme, P.; Arreghini, A.; Cacciato, A.; Breuil, L.; De Keersgieter, A.; Paraschiv, V.; Vrancken, C.; Douhard, B.; Richard, O.; Van Aerde, S.; Debusschere, I.; Van Houdt, J.
IEEE electron device letters, 11/2011, Letnik: 32, Številka: 11Journal Article
A vertical cylindrical SONOS cell with a novel bilayer polysilicon channel down to 22-nm diameter for 3-D NAND Flash memory is successfully developed. We introduce a thin amorphous silicon layer along with the oxide-nitride-oxide (ONO) gate stack inside the memory hole. This silicon layer protects the tunnel oxide during opening of the gate stack at the bottom of the memory hole, after which it serves as the first layer of the bilayer polysilicon channel. This approach enables the 3-D architecture to achieve minimum cell area (4 F 2 , with F being the feature size) without the need for the so-called pipeline connections. The smallest functional cells have the memory hole diameter F = 45 nm, resulting in 22-nm channel diameter. In case 16 cells are stacked, F = 45 nm would correspond to an equivalent 11-nm planar cell technology node. Excellent program/erase and retention obtained with the all-deposited ONO stack are demonstrated.
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JCR | SNIP | JCR | SNIP | JCR | SNIP | JCR | SNIP |
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in: SICRIS
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