Cross-sectioned silicon-on-insulator (SOI) wafers were examined by a combination of scanning probe techniques, namely scanning capacitance microscopy (SCM), scanning resistance microscopy (SRM) and Kelvin probe force microscopy (KFM). Tests were conducted using bonded SOI and separation by implanted oxygen (SIMOX) wafers. SCM images identified the depletion layer at the SOI–buried-oxide (BOX) interface, and the thickness of the depletion layer was found to vary according to the bias voltage applied to the Si substrate. SRM images identified the high-resistance region in the SOI wafers, and KFM resolved the charge distribution, revealing that SOI wafers hold inherent positive charge. The locations of positive charge accumulation were found to differ between the two types of SOI wafers. Based on the results of this study, the use of multiple scanning probe techniques represents a promising tool for sub-micron-scale electrical characterization of SOI wafers.