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  • Cascade delta-sigma modulator with pseudo-differential comparator-based switched-capacitor gain stage
    Prelog, Dušan, 1980- ...
    A low-power, multi-stage delta-sigma modulator with comparator-based switched-capacitor (CBSC) gain stages is presented. The presented design eliminates the need for operational amplifiers and ... replaces them by comparators with current sources at their outputs to alleviate the effects of continued technology scaling on analog and mixed-signal circuits. The proposed technique significantly reduces power consumption and can be applied to switched-capacitor delta-sigma modulators of arbitrary order. Based on the proposed methodology, a 2-1 cascade, single-bit, pseudo-differential switched-capacitor deltasigma modulator is developed and achieves a SNDR of 76.8 dB with an oversampling ratio of 64 at a clock frequency of 8 MHz.
    Source: Analog integrated circuits and signal processing. - ISSN 0925-1030 (Vol. 51, no. 3, 2007, str. 201-206)
    Type of material - article, component part
    Publish date - 2007
    Language - english
    COBISS.SI-ID - 11547926

    Link(s):

    http://www.springerlink.com/content/f4726680434m624k/fulltext.pdf

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