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Park, Myeong-Jae; Cho, Ho Sung; Yun, Tae-Sik; Byeon, Sangjin; Koo, Young Jun; Yoon, Sangsic; Lee, Dong Uk; Choi, Seokwoo; Park, Jihwan; Lee, Jinhyung; Cho, Kyungjun; Moon, Junil; Yoon, Byung-Kuk; Park, Young-Jun; Oh, Sang-muk; Lee, Chang Kwon; Kim, Tae-Kyun; Lee, Seong-Hee; Kim, Hyun-Woo; Ju, Yucheon; Lim, Seung-Kyun; Baek, Seung Geun; Lee, Kyo Yun; Lee, Sang Hun; We, Woo Sung; Kim, Seungchan; Choi, Yongseok; Lee, Seong-Hak; Yang, Seung Min; Lee, Gunho; Kim, In-Keun; Jeon, Younghyun; Park, Jae-Hyung; Yun, Jong Chan; Park, Chanhee; Kim, Sun-Yeol; Kim, Sungjin; Lee, Dong-Yeol; Oh, Su-Hyun; Hwang, Taejin; Shin, Junghyun; Lee, Yunho; Kim, Hyunsik; Lee, Jaeseung; Hur, Youngdo; Lee, Sangkwon; Jang, Jieun; Chun, Junhyun; Cho, Joohwan
2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022-Feb.-20, Volume: 65Conference Proceeding
Ever since the introduction of high bandwidth memory (HBM DRAM) and its succeeding line-ups, HBM DRAM has been heralded as a prominent solution to tackle the memory wall problem. However, despite continual memory advancements the advent of high-end systems, including supercomputers, hyper-scale data centers and machine learning accelerators, are expediting requirements for higher-performance memory solutions. To accommodate the increasing system-level demands, we introduce HBM3 DRAM, which employs multiple new features and design schemes. Techniques such as an on-die ECC engine, internal NN-DFE I/O signaling, TSV auto-calibration, and layout optimization based on machine-learning algorithms are implemented to efficiently control timing skew margins and SI degradation trade-offs. Furthermore, reduced voltage swings allow for improved memory bandwidth, density, power efficiency and reliability.
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