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  • Exploiting symbolic model checking for sensing stuck-at faults in digital circuits = Uporaba simboličnega preverjanja modelov pri zaznavanju zatičnih napak v digitalnih vezjih
    Časar, Aleš ; Brezočnik, Zmago ; Kapus, Tatjana
    This paper presents algorithms for automatic test pattern generation for discovering stuck-at faults in sequential digital circuits or proving that there are no stuck-at faults in the given circuit. ... A circuit is represented as a finite state machine. Properties for stuck-at faults expressed with CTL formulas which are valid in the circuit with stuck-at faults and generally not valid in the good circuit are generated. Validity of the formulas is checked by symbolic model checking, and for invalid formulas counterexamples are constructed which guide the circuit to the states which prove the absence of stuck-at faults. Test patterns guide the circuits exactly as the counterexamples. Experimental results for a set of benchmark circuits togetherwith the time and space complexity analysis of the algorithms are also given.
    Vir: Informacije MIDEM : časopis za mikroelektroniko, elektronske sestavne dele in materiale = časopis za mikroelektroniku, elektronske sastavne dijelove i materijale = journal of microelectronics, electronic components and materials. - ISSN 0352-9045 (Letn. 32, št. 3, sep. 2002, str. 171-180)
    Vrsta gradiva - članek, sestavni del
    Leto - 2002
    Jezik - angleški
    COBISS.SI-ID - 7703318

    Povezava(-e):

    Digitalna knjižnica Slovenije - dLib.si

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