In flip-chip design, voltage drop reduction in the power ground network has become a challenging problem particularly in the modern Multiple Supply Voltage(MSV) designs. An effective P/G network design and floorplanning- based solutions helps to produce a quality power plan in the layout. Hence, this paper proposes an iterative MSV floorplanning methodology that performs modifications in the existing floorplan representation that satisfies the voltage island constraint and produce an IR drop-aware quality layout. Furthermore, the proposed methodology is integrated with commercial tool design flow to analyze the reduction of IR drop in the layout. Two simulation-based experiments are performed in this paper to showcase the significance of this work. Firstly, it presents the simulation results that benchmark the proposed idealogy in non-flip chip designs. Secondly, the presented framework is integrated in flip-chip layouts of FIR design operating with two voltage islands for low power consumption. To understand the ability of the proposed floorplanning approach, the simulation were performed for two different sized P/G mesh structure for various mesh width. Experimental results from both simulations demonstrate that the proposed MSV floorplanning technique is effective in reducing IR drop while optimizing the design for low power dissipation.