Izvedba Viterbijevega dekodirnega algoritma s programirljivim vezjem FPGA; [Viterbi algorithm implementation on a FPGA programmable device] : diplomsko delo

Faculty of Electrical Engineering, Lj. (FERLJ)

Izvedba Viterbijevega dekodirnega algoritma s programirljivim vezjem FPGA = [Viterbi algorithm implementation on a FPGA programmable device] : diplomsko delo

Mejač, Rok

Type of material - undergraduate thesis ; adult, serious

Publication and manufacture - Ljubljana : [R. Mejač], 2011

Language - slovenian

COBISS.SI-ID - 8351316

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Call number – location, accession no. ...	Copy status	Reservation
FEa 0000007300 IN: 2008197 FEa 7300 IN: 2008197	available - reading room

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Year	Impact factor		Edition		Category		Classification
Year	JCR	SNIP	JCR	SNIP	JCR	SNIP	JCR	SNIP

Links to authors' personal bibliographies	Links to information on researchers in the SICRIS system
Mejač, Rok
Zajc, Matej	15752

Source: Personal bibliographies and: SICRIS

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