Short-circuit current calculation and its characteristic analysis are the foundation of selecting circuit breakers and designing protection systems. First, a companion circuit-based method is ...presented to fast calculate the short-circuit current of asymmetric bipolar modular multilevel converter-based multiterminal direct current (MMC-MTDC) grids. With the reduction of the whole MTDC grid into an equivalent RLC circuit, the short-circuit current of the grid is efficiently and accurately solved by companion circuit method instead of the numerical integration. In addition to the efficiency, the proposed method can readily adapt to various types of MTDC grids and all kinds of dc faults. Second, unique short-circuit current characteristics of a bipolar MTDC grid following different types of dc faults are theoretically analyzed. A fault type discrimination method is then proposed for bipolar MMC-MTDC grids with dedicated metallic return. Finally, intensive numerical results of two MTDC grids validate the accuracy, adaptability, and efficiency of the presented dc grid short-circuit current calculation method as well as the correctness of the short-circuit current characteristic analyses.
This study presents new low-power multiple-valued logic (MVL) circuits for nanoelectronics. These carbon nanotube field effect transistor (FET) (CNTFET)-based MVL circuits are designed based on the ...unique characteristics of the CNTFET device such as the capability of setting the desired threshold voltages by adopting correct diameters for the nanotubes as well as the same carrier mobility for the P- and N-type devices. These characteristics make CNTFETs very suitable for designing high-performance multiple-Vth circuits. The proposed MVL circuits are designed based on the conventional CMOS architecture and by utilising inherently binary gates. Moreover, each of the proposed CNTFET-based ternary circuits includes all the possible types of ternary logic, that is, negative, positive and standard, in one structure. The method proposed in this study is a universal technique for designing MVL logic circuits with any arbitrary number of logic levels, without static power dissipation. The results of the simulations, conducted using Synopsys HSPICE with 32 nm-CNTFET technology, demonstrate improvements in terms of power consumption, energy efficiency, robustness and specifically static power dissipation with respect to the other state-of-the-art ternary and quaternary circuits.
The rationale and development of a wafer-scale three-dimensional (3-D) integrated circuit technology are described. The essential elements of the 3-D technology are integrated circuit fabrication on ...silicon-on-insulator wafers, precision wafer-wafer alignment using an in-house-developed alignment system, low-temperature wafer-wafer bonding to transfer and stack active circuit layers, and interconnection of the circuit layers with dense-vertical connections with sub-Omega 3-D via resistances. The 3-D integration process is described as well as the properties of the four enabling technologies. The wafer-scale 3-D technology imposes constraints on the placement of the first lithographic level in a wafer-stepper process. Control of wafer distortion and wafer bow is required to achieve submicrometer vertical vias. Three-tier digital and analog 3-D circuits were designed and fabricated. The performance characteristics of a 3-D ring oscillator, a 1024 times 1024 visible imager with an 8-mum pixel pitch, and a 64 times 64 Geiger-mode laser radar chip are described
Energy performance requirements are causing designers of next-generation systems to explore approaches to lowest possible power consumption. Subthreshold operation is being examined to stretch ...low-power circuit designs beyond the normal modes of operation, with the potential for large energy savings. Some of the challenges to be overcome, like 10-100× performance penalties, are being addressed by research into parallelism. However, the uncertainty in timing generated by operating in subthreshold represents a major challenge to overcome. In this paper, first, we will introduce some background information on digital logic subthreshold operation, then provide some background on clockless logic design approaches giving a brief overview of some of the characteristics of the different design styles and focusing on NULL convention logic. Next, we will examine the application of that clockless logic approach to a military system, reviewing the background of the experiment, factors considered in the comparison, and then summarizing the results of the comparisons. Finally, an overview of additional research and development that will be needed to make the technique available to subthreshold designers is presented.
Negative-bias-temperature instability (NBTI) has become the primary limiting factor of circuit life time. In this paper, we develop a hierarchical framework for analyzing the impact of NBTI on the ...performance of logic circuits under various operation conditions, such as the supply voltage, temperature, and node switching activity. Given a circuit topology and input switching activity, we propose an efficient method to predict the degradation of circuit speed over a long period of time. The effectiveness of our method is comprehensively demonstrated with the International Symposium on Circuits and Systems (ISCAS) benchmarks and a 65-nm industrial design. Furthermore, we extract the following key design insights for reliable circuit design under NBTI effect, including: 1) During dynamic operation, NBTI-induced degradation is relatively insensitive to supply voltage, but strongly dependent on temperature; 2) There is an optimum supply voltage that leads to the minimum of circuit performance degradation; circuit degradation rate actually goes up if supply voltage is lower than the optimum value; 3) Circuit performance degradation due to NBTI is highly sensitive to input vectors. The difference in delay degradation is up to 5× for various static and dynamic operations. Finally, we examine the interaction between NBTI effect, and process and design uncertainty in realistic conditions.
This work introduces the use of compressed sensing (CS) algorithms for data compression in wireless sensors to address the energy and telemetry bandwidth constraints common to wireless sensor nodes. ...Circuit models of both analog and digital implementations of the CS system are presented that enable analysis of the power/performance costs associated with the design space for any potential CS application, including analog-to-information converters (AIC). Results of the analysis show that a digital implementation is significantly more energy-efficient for the wireless sensor space where signals require high gain and medium to high resolutions. The resulting circuit architecture is implemented in a 90 nm CMOS process. Measured power results correlate well with the circuit models, and the test system demonstrates continuous, on-the-fly data processing, resulting in more than an order of magnitude compression for electroencephalography (EEG) signals while consuming only 1.9 μW at 0.6 V for sub-20 kS/s sampling rates. The design and measurement of the proposed architecture is presented in the context of medical sensors, however the tools and insights are generally applicable to any sparse data acquisition.
In recent years, dc distribution grids have become increasingly popular because of the interest in the diffusion of distributed renewable energy. In this scenario, dc distribution grids are also ...favored because of the increased use of batteries and power electronic loads. The main limit to the spread of dc grids is their protection devices, which still present several problems. At present, protection devices are represented by traditional mechanical breakers or static electronic components. The first, which interrupt dc currents, have good reliability but need maintenance and have long intervention periods. In contrast, electronic switches are fast and reliable, but they reduce the efficiency because of their voltage drop. In this scenario, some hybrid breakers have been proposed to obtain the advantages of both devices. The previous solutions of hybrid breakers still suffer several critical issues and, usually, are not capable of protecting a system from short circuits without significantly reducing their lifetime. In this paper, a new low-voltage hybrid circuit breaker topology is proposed. The procedure to dimension all of the active and passive components in the device is analyzed, and the effectiveness of the proposed solution is proven by means of experimental results obtained using a prototype.
Linear Circuit Design Handbook Analog Devices Inc., Engineeri; Zumbahlen, Hank
2011, 2008, 2011-08-30T00:00:00, 2011-08-30, c2008
eBook
This book enables design engineers to be more effective in designing discrete and integrated circuits by helping them understand the role of analog devices in their circuit design. Analog elements ...are at the heart of many important functions in both discrete and integrated circuits, but from a design perspective the analog components are often the most difficult to understand. Examples include operational amplifiers, D/A and A/D converters and active filters. Effective circuit design requires a strong understanding of the operation of these analog devices and how they affect circuit design. * Comprehensive coverage of analog circuit components for the practicing engineer Market-validated design information for all major types of linear circuits Includes practical advice on how to read op amp data sheets and how to choose off-the-shelf op amps Full chapter covering printed circuit board design issues
This work presents the design and characterization of an ultralow-power core chip for electronically scanned arrays at <inline-formula> <tex-math notation="LaTeX">X </tex-math></inline-formula>-band, ...implemented in 0.25-/0.5-<inline-formula> <tex-math notation="LaTeX">{\mu }\text{m} </tex-math></inline-formula> E-/D-mode gallium arsenide (GaAs) pHEMT technology. In particular, design details are given about the two core functional blocks embedded in the microwave monolithic integrated circuit (MMIC): a 12-bit phase and amplitude control circuit and an 18-bit serial-to-parallel (S2P) interface. The S2P interface was designed resorting to a custom symmetric device model, expressly conceived for the time-domain simulations required for digital circuits. Due to the adoption of a differential structure with resistive pull-ups, it achieves a state-of-the-art power consumption of 2.2 mW/bit and nearly 87% yield. The analog circuit includes a 6-bit phase shifter (PS) and a 6-bit attenuator. To mitigate risks, two different PS architectures have been developed and are compared in this work, discussing advantages and drawbacks of the different solutions. Since the two designs share the same target specifications, a truly fair comparison can be made not only in terms of performance but also concerning robustness and repeatability, thus providing useful guidelines for the selection of the most appropriate strategy. In particular, it is shown that one architecture outperforms the other by about 2 dB and 1.5° in terms of insertion loss and rms phase error, respectively.
Reliable operation of dc-dc converters is vital for many applications. An appropriate converter monitoring scheme is required for fault detection and adoption of effective remedial strategies. Switch ...faults and degradation of electrolytic capacitor account for a considerable portion of the converter failures. Although rate of diode failures is not remarkable, power switch may be damaged in case of diode fault occurrence. Furthermore, for applications in which a redundant switch is employed as a remedy, it will be also endangered by diode failures if diode fault detection has not been considered in the monitoring scheme. Therefore, diode condition monitoring improves reliability of the converter monitoring approaches. This paper presents a simple diagnosis technique for open-circuit and short-circuit faults of the switch and diode in nonisolated dc-dc converters. The technique only employs diode voltage as the detection signature. The diode voltage and gate driver signal are processed in a simple logic circuit to generate some indicators for switch and diode fault diagnosis. Basis of the technique is discussed in detail. Several experiments have been carried out on buck, boost, and buck-boost converters. The results confirm the technique capability for switch and diode fault diagnosis in less than one switching cycle.
PDF
