The communication architectures in modern SoCs (system-on-chip) not only impact the performance of SoC considerably, but also consume a large amount of the design cycle. This paper presents a novel methodology to synthesize crossbar bus communication architecture on transaction level using genetic algorithm. This methodology first clusters slave modules using a static communication traffic balancing algorithm (SCTBA). Then it uses genetic algorithm (GA) to configure communication parameters and verifies communication delay by transaction level modeling (TLM) and simulation. Finally it outputs the optimal partial crossbar bus topology and communication parameters satisfying the communication delay constraint. The experimental case studies show that our communication synthesis methodology results in up to 5x reduction in synthesis time and 1.5x component savings when compared to the methodologies ever before.