With continuous evolution of semiconductor process technologies and IC (Integrated Chip) scales, more and more complex functions are integrated. Multi-core multi-thread CPU (Central Processing Unit), multi-dimension NoC (Network on Chip), high speed interfaces, kinds of peripherals and so on IP (Intellectual Property) are integrated into SoC (System on Chip). As a result, verification scenarios during IC development become extremely complicated, which leads to great challenges to the SoC development and corresponding verification completeness. Currently PSS (Portable Test Stimulus Standard) has been introduced along with the UVM (Universal Verification Methodology) for generating extensive randomized stimulus with more complicated scenarios.