This paper presents a four-level pulse amplitude modulation (PAM4) quarter-rate receiver that efficiently compensates for moderate channel loss in a robust manner through background adaptation of the ...receiver thresholds and equalization taps. The front-end utilizes an input single-stage continuous-time linear equalizer (CTLE) to boost the main cursor and relax the pre-cursor cancellation requirement, requiring only a 2-tap pre-cursor feed-forward equalizer (FFE) on the transmitter side. A 2-tap decision feedback equalizer (DFE) follows that includes one finite impulse response (FIR) tap and one infinite impulse response (IIR) tap to cancel first post-cursor and long-tail inter-symbol interference (ISI), respectively. In addition to the per-slice main three data samplers, a single error sampler is utilized for background threshold control and an edge-based sampler performs both phase-locked loop (PLL)-based clock and data recovery (CDR) phase detection and generates information for background DFE tap adaptation. Fabricated in general purpose (GP) 65-nm CMOS, the 56-Gb/s receiver achieves 4.63 mW/Gb/s and compensates for up to 20.8-dB loss at a bit error rate (BER) <; 10 -12 when operated with a 2-tap FFE transmitter.
A 10-bit 80-MS/s analog-to-digital converter (ADC) with an area- and power-efficient architecture is described. By sharing an amplifier between two successive pipeline stages, a 10-bit pipeline is ...realized using just four amplifiers with a separate sample-and-hold block. The proposed feedback signal polarity inverting (FSPI) technique addresses the drawback of the conventional amplifier sharing technique. A wide-swing wide-bandwidth telescopic amplifier and an early comparison technique with a constant delay circuit have been developed to further reduce power consumption. The ADC is implemented in a 0.18-/spl mu/m dual-gate-oxidation CMOS process technology, achieves 72.8-dBc spurious free dynamic range, 57.92-dBc signal-to-noise ratio, 9.29 effective number of bits (ENOB) for a 99-MHz input at full sampling rate, and consumes 69 mW from a 3-V supply. The ADC occupies 1.85 mm/sup 2/.
A PAM4 quarter-rate receiver employs a singlestage CTLE and a DFE with 1 FIR and 1 IIR-taps to efficiently compensate for channel loss. In addition to the per-slice main 3 data samplers, an error ...sampler is utilized for background threshold control and an edge-based sampler performs both PLL-based CDR phase detection and generates information for background DFE tap adaptation. Fabricated in GP 65nm CMOS, the 56Gb/s receiver achieves 4.63mW/Gb/s and compensates for up to 20.8dB loss when operated with a 2-tap FFE transmitter.
An analysis of charge pump design for improved radiation tolerance of phase locked loops is presented. Two radiation-hardened-by-design approaches are considered to mitigate the total ionizing dose ...damage of the circuit, and a thick-film SOI SiGe process technology has been used to reduce charge collection of single event strikes. The results show that a modified design approach to implement the charge pump using SiGe HBTs can provide advantages in radiation tolerance to improve tri-state leakage performance, particularly for missions expecting large accumulated doses.
The process of troubleshooting a 12.5Gbps SFF-8431 channel return loss compliance failure is described in details. Excellent simulation to measurement correlation has been achieved after capturing a ...capacitive dip at the package/PCB interface ("phantom" capacitance) with package and board physical layout geometries merged into one single electromagnetic simulation. Source of the "phantom" capacitance is identified and explained. Design techniques to circumvent the "phantom" capacitance and their effectiveness are evaluated through simulation studies and measurements.
A bandgap reference circuit is presented in a 0.13 /spl mu/m process. Switching techniques are used to eliminate the effects of mismatch in the op amp and current source devices. A novel leakage ...current compensation technique allows bandgap operation to 200/spl deg/C. The circuit demonstrates a variation of 1.6 mV over 150/spl deg/C and has a temperature coefficient of 13.3 ppm//spl deg/C. A digital control block necessary for the switching technique is also presented.
