The NA62 experiment is designed to measure the (ultra-)rare decay K+→π+νν¯ branching ratio with a precision of ∼10% at the CERN Super Proton Synchrotron (SPS). The L0 Trigger Processor (L0TP) is the ...lowest level system of the trigger chain. It is hardware implemented using programmable logic. The architecture of the L0TP is completely new for a high energy physics experiment. It is fully digital, based on a standard gigabit ethernet communication between detectors and L0TP Board. The L0TP Board is a commercial development board, Terasic DE4, mounting an Altera Stratix IV FPGA. The primitives generated by sub-detectors are sent asynchronously using the UDP protocol to the L0TP during the entire beam spill period (about 5 seconds). The L0TP realigns in time the primitives coming from 7 different sources and manages the information of the time plus all the characteristics of the event as energy, multiplicity and position of hits in order to select good events with a comparison with preset masks. It should guarantee a maximum latency of 1ms. The maximum input rate is 10MHz for each sub-detector, while the design maximum output trigger rate is 1MHz. A complete trigger-less parasitic acquisition of the primitives is possible using mirroring switches to monitor the L0 behavior. A first version of the L0TP was commissioned during the 2014 NA62 pilot run and it is used in the current data taking. A description of the trigger algorithm is here presented.
The Level 0 Trigger Processor for the NA62 experiment Chiozzi, S.; Gamberini, E.; Gianoli, A. ...
Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment,
07/2016, Letnik:
824
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In the NA62 experiment at CERN, the intense flux of particles requires a high-performance trigger for the data acquisition system. A Level 0 Trigger Processor (L0TP) was realized, performing the ...event selection based on trigger primitives coming from sub-detectors and reducing the trigger rate from 10 to 1MHz. The L0TP is based on a commercial FPGA device and has been implemented in two different solutions. The performance of the two systems are highlighted and compared.
The Gigatracker, the silicon beam tracker for the NA62 experiment at CERN Federici, L.; Aglieri Rinella, G.; Alvarez Feito, D. ...
Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment,
04/2020, Letnik:
958
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The Gigatracker is the NA62 beam tracker. It is made of three 63.1mm×29.3mm stations of 300μm×300μm hybrid silicon pixel detectors installed in vacuum (∼10−6mbar). The beam particles, flowing at ...750MHz, are traced in 4-dimensions by mean of time-stamping pixels with a design resolution of 200ps. This performance has to be maintained despite the beam irradiation amounting to a yearly fluence of 2×10141MeVneq∕cm2. The detector material minimization is paramount, as the detector faces the full beam. The station material budget is reduced to 0.5%X0 by using (HEP world first) micro-channels cooling. We will describe the detector design and performances during the NA62 runs.
The NA62 GigaTracker Aglieri Rinella, G.; Feito, D. Alvarez; Arcidiacono, R. ...
Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment,
02/2017, Letnik:
845
Journal Article
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The GigaTracker is a hybrid silicon pixel detector built for the NA62 experiment aiming at measuring the branching fraction of the ultra-rare kaon decay K+→π+νν¯ at the CERN SPS. The detector has to ...track particles in a beam with a flux reaching 1.3MHz/mm2 and provide single-hit timing with 200ps RMS resolution for a total material budget of less than 0.5% X0 per station. The tracker comprises three 60.8mm×27mm stations installed in vacuum (∼10−6mbar) and cooled with liquid C6F14 circulating through micro-channels etched inside a few hundred micron thick silicon plates. Each station is composed of a 200μm thick silicon sensor read out by 2×5 custom 100μm thick ASICs, called TDCPix. Each chip contains 40×45 asynchronous pixels, 300μm×300μm each and is instrumented with 100ps bin time-to-digital converters. In order to cope with the high rate, the TDCPix is equipped with four 3.2Gb/s serialisers sending out the data. We will describe the detector and the results from the 2014 and 2015 NA62 runs.
Micro Pattern Gas Detectors (MPGD) are the new frontier in gas trackers. Among this kind of devices, the Gas Electron Multiplier (GEM) chambers are widely used. The experimental signals acquired with ...the detector must obviously be reconstructed and analysed. In this contribution, a new offline software to perform reconstruction, alignment and analysis on the data collected with APV-25 and TIGER ASICs will be presented. GRAAL (Gem Reconstruction And Analysis Library) is able to measure the performance of a MPGD detector with a strip segmented anode (presently). The code is divided in three parts: reconstruction, where the hits are digitized and clusterized; tracking, where a procedure fits the points from the tracking system and uses that information to align the chamber with rotations and shifts; analysis, where the performance is evaluated (e.g. efficiency, spatial resolution,etc.). The user must set the geometry of the setup and then the program returns automatically the analysis results, taking care of different conditions of gas mixture, electric field, magnetic field, geometries, strip orientation, dead strip, misalignment and many others.
Graphical processors for HEP trigger systems Ammendola, R.; Biagioni, A.; Chiozzi, S. ...
Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment,
02/2017, Letnik:
845
Journal Article
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General-purpose computing on GPUs is emerging as a new paradigm in several fields of science, although so far applications have been tailored to employ GPUs as accelerators in offline computations. ...With the steady decrease of GPU latencies and the increase in link and memory throughputs, time is ripe for real-time applications using GPUs in high-energy physics data acquisition and trigger systems. We will discuss the use of online parallel computing on GPUs for synchronous low level trigger systems, focusing on tests performed on the trigger of the CERN NA62 experiment. Latencies of all components need analysing, networking being the most critical. To keep it under control, we envisioned NaNet, an FPGA-based PCIe Network Interface Card (NIC) enabling GPUDirect connection. Moreover, we discuss how specific trigger algorithms can be parallelised and thus benefit from a GPU implementation, in terms of increased execution speed. Such improvements are particularly relevant for the foreseen LHC luminosity upgrade where highly selective algorithms will be crucial to maintain sustainable trigger rates with very high pileup.
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