RISC-V is a modern Instruction Set Architecture (ISA) that, by its open nature in combination with a clean and modular design, has enormous potential to become a game changer in the Internet of ...Things (IoT) era. Recently, SystemC-based Virtual Prototypes (VPs) have been introduced into the RISC-V ecosystem to lay the foundation for advanced industry-proven system-level use-cases. However, VP-driven environment modeling and interaction have mostly been neglected in the RISC-V context. In this paper, we propose such an extension to broaden the application domain for virtual prototyping in the RISC-V context. As a foundation, we built upon the open source RISC-V VP available at GitHub. For a visualization of the environment purposes, we designed a Graphical User Interface (GUI) and designed appropriate libraries to offer hardware communication interfaces such as GPIO and SPI from the VP to an interactive environment model. Our approach is designed to be integrated with SystemC-based VPs that leverage a Transaction-Level Modeling (TLM) communication system to prefer a speed-optimized simulation. To show the practicability of an environment model, we provide a set of building blocks such as buttons, LEDs and an OLED display and configured them in two demonstration environments. Moreover, for rapid prototyping purposes, we provide a modeling layer that leverages the dynamic Lua scripting language to design components and integrate them with the VP-based simulation. Our evaluation with two different case-studies demonstrates the applicability of our approach in building virtual environments effectively and correctly when matching the real physical systems. To advance the RISC-V community and stimulate further research, we provide our extended VP platform with the environment configuration and visualization toolbox, as well as both case-studies as open source on GitHub.
RISC-V is gaining huge popularity in particular for embedded systems. Recently, a SystemC-based Virtual Prototype (VP) has been open sourced to lay the foundation for providing support for ...system-level use cases such as design space exploration, analysis of complex HW/SW interactions and power/timing/performance validation for RISC-V based systems.In this paper, we propose an efficient core timing model and integrate it into the VP core to enable fast and accurate performance evaluation for RISC-V based systems. As a case-study we provide a timing configuration matching the RISC-V HiFive1 board from SiFive. Our experiments demonstrate that our approach allows to obtain very accurate performance evaluation results while still retaining a high simulation performance.
In this paper, we propose a Virtual Prototype (VP) driven verification methodology for Hardware (HW) peripherals. In particular, we combine two approaches that complement each other and use the VP as ...a readily available reference model: We use (A) Coverage-Guided Fuzzing (CGF) which enables comprehensive verification at the unit-level of the Register-Transfer Level (RTL) HW peripheral with a Transaction Level Modeling (TLM) reference, and (B) an application-driven co-simulation-based approach that enables verification of the HW peripheral at the system-level. As a case-study, we utilize a RISC-V Platform Level Interrupt Controller (PLIC) as HW peripheral and use an abstract TLM PLIC implementation from the open source RISC-V VP as the reference model. In our experiments we find three behavioral mismatches and discuss the observation of these, as well as non-functional timing behavior mismatches, that were found through the proposed synergistic approach. Furthermore, we provide a discussion and considerations on the RTL/TLM Transactors, as they embody one keystone in cross-level methods. As the different approaches uncover different mismatches in our case-study (e.g., behavioral mismatches and timing mismatches), we conclude a synergy between the methods to aid in verification efforts.
Approximate Computing (AC) is a design paradigm that makes use of the error tolerance inherited by many applications. The goal of AC is to trade off accuracy for performance in terms of computation ...time, energy consumption and/or hardware complexity.In the field of circuit design for AC, error-metrics are used to express the degree of approximation. Evaluating these error-metrics is a key challenge. Several approaches exist, however, to this day not all relevant metrics can be evaluated with formal methods. Recently, Symbolic Computer Algebra (SCA) has been used to evaluate error-metrics during approximate hardware generation. In this paper, we generalize the idea to use SCA and propose a methodology which is suitable for formal evaluation of all established error-metrics. This approach can be divided into three stages: 1) Determine the remainder of the AC circuit wrt. the specification using SCA, 2) build an Algebraic Decision Diagram (ADD) to represent the remainder and 3) evaluate each error-metric by a tailored ADD traversal algorithm. In the experiments, we apply our algorithms to a large and well-known benchmark set.
The complexity of Magnetic Resonance Imaging (MRI) sequences requires expert knowledge about the underlying contrast mechanisms to select from the wide range of available applications and protocols. ...Automation of this process using machine learning (ML) can support the radiologists and MR technicians by complementing their experience and finding the optimal MRI sequence and protocol for certain applications.
We define domain-specific languages (DSL) both for describing MRI sequences and for formulating clinical demands for sequence optimization. By using various abstraction levels, we allow different key users exact definitions of MRI sequences and make them more accessible to ML. We use a vendor-independent MRI framework (gammaSTAR) to build sequences that are formulated by the DSL and export them using the generic file format introduced by the Pulseq framework, making it possible to simulate phantom data using the open-source MR simulation framework JEMRIS to build a training database that relates input MRI sequences to output sets of metrics. Utilizing ML techniques, we learn this correspondence to allow efficient optimization of MRI sequences meeting the clinical demands formulated as a starting point.
ML methods are capable of capturing the relation of input and simulated output parameters. Evolutionary algorithms show promising results in finding optimal MRI sequences with regards to the training data. Simulated and acquired MRI data show high correspondence to the initial set of requirements.
This work has the potential to offer optimal solutions for different clinical scenarios, potentially reducing exam times by preventing suboptimal MRI protocol settings. Future work needs to cover additional DSL layers of higher flexibility as well as an optimization of the underlying MRI simulation process together with an extension of the optimization method.
The emergence of virtual prototypes (VPs) at the electronic system level (ESL) has played a major role in modernizing the system-on-chips (SoCs) design process to raise design productivity and reduce ...time-to-market. A VP is an abstract and executable software model implemented typically using SystemC and its transaction-level modeling (TLM) framework. However, this modern VP-based design process still has weaknesses, in particular, due to the significant manual effort involved for design understanding, analysis, and modeling tasks which is both time consuming and error-prone. This article introduces an automated and fast design understanding approach that enables designers to trace detailed information of the VPs' structure and behavior. Experimental results including a real-world VP-based SoC show the advantages of our approach, such as its accuracy, applicability, and scalability.
ATPG based on Boolean satisfiability (SAT) turned out to be a robust alternative to classical structural automatic test pattern generation (ATPG) algorithms performing very well especially for ...hard-to-detect faults but suffer from the overhead for easy-to-detect faults. In this letter, we propose new efficient data structures and methodologies for SAT-based ATPG. The novel incremental SAT solving technique dynamic clause activation which makes use of structural information using dedicated data structures forms the core of a new flexible SAT-based ATPG approach. Experimental results on large industrial circuits show a significant performance gain and a removal of the limitations. At the same time, the robustness of SAT-based ATPG can even be strengthened resulting in very high fault efficiency and increased fault coverage for transition faults.
Although researchers and engineers originally focused on a preponderantly irreversible computing paradigm, alternative models receive more and more attention. Reversible computation is a promising ...example which has applications in many emerging technologies such as quantum computation or alternative directions for low-power design. Accordingly, the design of reversible circuits has become an intensely studied research area. In particular, the efficient synthesis of complex reversible circuits poses an important and difficult research question. Most of the solutions proposed thus far are based on pure Boolean function representations such as truth tables or decision diagrams.
In this paper, we provide a comprehensive introduction to and present extensions for the hardware description language SyReC which allows for the specification and automatic synthesis of reversible circuits. Besides a detailed presentation of the language׳s concepts and operations, we additionally propose algorithms that optimize the resulting circuits with respect to different objectives. A case study on a RISC CPU as well as a thorough experimental evaluation of both, the synthesis approach and its optimizations, show the applicability and demonstrate the advantage of SyReC compared to other solutions based on Boolean function representations.
•Definition of a hardware description language for reversible circuits.•Introduction of a synthesis methodology which realizes a corresponding description as a reversible circuit.•Introduction of refinements of the synthesis methodology with respect to different cost metrics.•Evaluation and case studies of the hardware description language as well as the synthesis results.
Automatic Fault Localization for Property Checking Fey, G.; Staber, S.; Bloem, R. ...
IEEE transactions on computer-aided design of integrated circuits and systems,
06/2008, Letnik:
27, Številka:
6
Journal Article
Recenzirano
We present an efficient fully automatic approach to fault localization for safety properties stated in linear temporal logic. We view the failure as a contradiction between the specification and the ...actual behavior and look for components that explain this discrepancy. We find these components by solving the satisfiability of a propositional Boolean formula. We show how to construct this formula and how to extend it so that we find exactly those components that can be used to repair the circuit for a given set of counterexamples. Furthermore, we discuss how to efficiently solve the formula by using the proper decision heuristics and simulation-based preprocessing. We demonstrate the quality and efficiency of our approach by experimental results.
