Direct ionization from low energy protons is shown to cause upsets in a 65-nm bulk CMOS SRAM, consistent with results reported for other deep submicron technologies. The experimental data are used to ...calibrate a Monte Carlo rate prediction model, which is used to evaluate the importance of this upset mechanism in typical space environments. For the ISS orbit and a geosynchronous (worst day) orbit, direct ionization from protons is a major contributor to the total error rate, but for a geosynchronous (solar min) orbit, the proton flux is too low to cause a significant number of events. The implications of these results for hardness assurance are discussed.
Experimental results are presented on single-bit-upsets (SBU) and multiple-bit-upsets (MBU) on a 45 nm SOI SRAM. The accelerated testing results show the SBU-per-bit cross section is relatively ...constant with technology scaling but the MBU cross section is increasing. The MBU data show the importance of acquiring and analyzing the data with respect to the location of the multiple-bit upsets since the relative location of the cells is important in determining which MBU upsets can be corrected with error correcting code (ECC) circuits. For the SOI SRAMs, a large MBU orientation effect is observed with most of the MBU events occurring along the same SRAM bit-line; allowing ECC circuits to correct most of these MBU events.
Experimental results are presented on proton induced single-event-upsets (SEU) on a 65 nm silicon-on-insulator (SOI) SRAM. The low energy proton SEU results are very different for the 65 nm SRAM as ...compared with SRAMs fabricated in previous technology generations. Specifically, no upset threshold is observed as the proton energy is decreased down to 1 MeV; and a sharp rise in the upset cross-section is observed below 1 MeV. The increase below 1 MeV is attributed to upsets caused by direct ionization from the low energy protons. The implications of the low energy proton upsets are discussed for space applications of 65 nm SRAMs; and the implications for radiation assurance testing are also discussed.
Single event upset (SEU) experimental heavy ion data and modeling results for CMOS, silicon-on-insulator (SOI), 32 nm and 45 nm stacked and DICE latches are presented. Novel data analysis is shown to ...be important for hardness assurance where Monte Carlo modeling with a realistic heavy ion track structure, along with a new visualization aid (the Angular Dependent Cross-section Distribution, ADCD), allows one to quickly assess the improvements, or limitations, of a particular latch design. It was found to be an effective technique for making SEU predictions for alternative 32 nm SOI latch layouts.
The effects of device orientation on heavy ion-induced multiple-bit upset (MBU) in 65 nm SRAMs are examined. The MBU response is shown to depend on the orientation of the device during irradiation. ...The response depends on the direction of the incident ion to the n- and p-wells of the SRAM. The MBU response is simulated using Monte Carlo methods for a space environment. The probability is calculated for event size. Single-bit upsets in the space environment account for 90% of all events with exponentially decreasing probabilities of larger MBU events.
Heavy ion data for custom SRAMs fabricated in a 45-nm CMOS technology demonstrate the effects of N- and P-well contact densities on single-event latchup. Although scaling has improved latchup ...robustness, process-level immunity has not been achieved, indicating a continued need for latchup mitigation techniques. A simple, algorithmic approach for selecting N- and P-well contact densities is described that ensures latchup immunity while minimizing the area penalty.
Pulsed laser test results for NAND flash memories are compared with broad beam heavy ion results and also with heavy ion results obtained with the collimated Milli-Beam™ source. The pulsed laser ...measurements reported here, with smaller focused spot sizes and as a function of the incident pulse energy, serve to reconcile the previously reported inconsistencies. The Milli-Beam™ and pulsed laser results appear to be consistent, and differences from the broad beam heavy ion results can be explained. The results suggest that the high current SEFIs reported by us and others arise from multiple ion (or multiple photon) interactions, and are not associated with single ion strikes.
We report on complementary use of two-photon absorption laser and heavy-ion SEE testing to evaluate the single-event response of SDRAMs. The tandem testing technique helps disentangle the response of ...devices exhibiting multiple SEE modes.
We have compared the data retention of irradiated commercial NAND flash memories at different doses. Activation energies for retention testing at high temperature have also been determined.
A well-collapse source-injection mode for SRAM SEU is demonstrated through TCAD modeling. The recovery of the SRAM's state is shown to be based upon the resistive path from the p+ -sources in the ...SRAM to the well. Multiple cell upset patterns for direct charge collection and the well-collapse source-injection mechanisms are predicted and compared to SRAM test data.
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