Charge trapping at oxide defects fundamentally affects the reliability of MOS transistors. In particular, charge trapping has long been made responsible for random telegraph and 1/
f noise. Recently, ...it has been identified as a significant contributor to bias temperature instabilities. Conventional defect models assume that the defect has two states, one of them neutral and the other charged. The transition rates between the two states are calculated using some extended Shockley–Read–Hall theory, which neglects the configurational changes occurring at the defect site following a charge trapping or emission event. In order to capture these changes, multiphonon models have been in use for many decades but have not found their way into the mainstream of reliability modeling yet. Furthermore, recent experimental results demonstrate that defects have more states than the two assumed in the conventional model. These additional states together with multiphonon charge transfer mechanisms are essential for the understanding of the complex defect dynamics. The present review summarizes the basic principles of how to model stochastic defect transitions with a particular focus on multi-state defects. After discussing the limitations of Shockley–Read–Hall theory, the relatively simple semiclassical approximation of multiphonon theory is introduced which already provides a much better description. Finally, the transition rates for multi-state defects are estimated using multiphonon theory, which gives a very accurate description of the latest experimental data.
Nanoelectronic devices based on 2D materials are far from delivering their full theoretical performance potential due to the lack of scalable insulators. Amorphous oxides that work well in silicon ...technology have ill-defined interfaces with 2D materials and numerous defects, while 2D hexagonal boron nitride does not meet required dielectric specifications. The list of suitable alternative insulators is currently very limited. Thus, a radically different mindset with respect to suitable insulators for 2D technologies may be required. We review possible solution scenarios like the creation of clean interfaces, production of native oxides from 2D semiconductors and more intensive studies on crystalline insulators.
Negative bias temperature instability is regarded as one of the most important reliability concerns of highly scaled PMOS transistors. As a consequence of the continuous downscaling of semiconductor ...devices this issue has become even more important over the last couple of years due to the high electric fields in the oxide and the routine incorporation of nitrogen. During negative bias temperature stress a shift in important parameters of PMOS transistors, such as the threshold voltage, subthreshold slope, and mobility is observed. Modeling efforts date back to the reaction-diffusion model proposed by Jeppson and Svensson thirty years ago which has been continuously refined since then. Although the reaction-diffusion model is able to explain many experimentally observed characteristics, some microscopic details are still not well understood. Recently, various alternative explanations have been put forward, some of them extending, some of them contradicting the standard reaction-diffusion model. We review these explanations with a special focus on modeling issues.
One of the most important degradation modes in CMOS technologies, the bias temperature instability (BTI) has been known since the 1960s. Already in early interpretations, charge trapping in the oxide ...was considered an important aspect of the degradation. In their 1977 paper, Jeppson and Svensson suggested a hydrogen-diffusion controlled mechanism for the creation of interface states. Their reaction-diffusion model subsequently became the dominant explanation of the phenomenon. While Jeppson and Svensson gave a preliminary study of the recovery of the degradation, this issue received only limited attention for many years. In the last decade, however, a large number of detailed recovery studies have been published, showing clearly that the reaction-diffusion mechanism is inconsistent with the data. As a consequence, the research focus shifted back toward charge trapping. Currently available advanced charge-trapping theories based on switching oxide traps are now able to explain the bulk of the experimental data. We give a review of our perspective on some selected developments in this area.
We investigate the temperature accelerated recovery from hot-carrier (HC) damage with the help of local polycrystalline heating structures in n-MOSFETs designed for power applications. These devices ...have a rather thick gate oxide and long channel, which assures that mainly interface traps are created through the HC stress. We further verify with frequency-dependent charge pumping that in our devices border traps are of vanishing importance compared to interface traps. We analyze the time and temperature dependence of the recovery of the interface traps after HC stress using models from the literature. The data are fairly consistent with the assumption of interfacial silicon dangling bonds that become passivated by hydrogen. The forward passivation energy is found to be normally distributed because of the distribution of atomic defect configurations. The distribution parameters are independent of the overall degradation level which shows that the passivation process is limited by the bond association kinetics rather than hydrogen supply. Our results are of importance for HC research as well as for the ongoing discussion regarding the quasi-permanent component of bias temperature instability.
For ultra-scaled technology nodes at channel lengths below 12 nm, two-dimensional (2D) materials are a potential replacement for silicon since even atomically thin 2D semiconductors can maintain ...sizable mobilities and provide enhanced gate control in a stacked channel nanosheet transistor geometry. While theoretical projections and available experimental prototypes indicate great potential for 2D field effect transistors (FETs), several major challenges must be solved to realize CMOS logic circuits based on 2D materials at the wafer scale. This review discusses the most critical issues and benchmarks against the targets outlined for the 0.7 nm node in the International Roadmap for Devices and Systems scheduled for 2034. These issues are grouped into four areas; device scaling, the formation of low-resistive contacts to 2D semiconductors, gate stack design, and wafer-scale process integration. Here, we summarize recent developments in these areas and identify the most important future research questions which will have to be solved to allow for industrial adaptation of the 2D technology.
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