Industrial plants suffer from a high degree of complexity and incompatibility in their communication infrastructure, caused by a wild mix of proprietary technologies. This prevents transformation ...towards Industry 4.0 and the Industrial Internet of Things. Open Platform Communications Unified Architecture (OPC UA) is a standardized protocol that addresses these problems with uniform and semantic communication across all levels of the hierarchy. However, its adoption in embedded field devices, such as sensors and actors, is still lacking due to prohibitive memory and power requirements of software implementations. We have developed a dedicated hardware engine that offloads processing of the OPC UA protocol and enables realization of compact and low-power field devices with OPC UA support. As part of a proof-of-concept embedded system we have implemented this engine in a 22 nm FDSOI technology. We measured performance, power consumption, and memory footprint of our test chip and compared it with a software implementation based on open62541 and a Raspberry Pi 2B. Our OPC UA hardware engine is 50 times more energy efficient and only requires 36 KiB of memory. The complete chip consumes only 24 mW under full load, making it suitable for low-power embedded applications.
This paper addresses efficient DC-DC converters for neural recording and processing implants in 22 nm FDSOI from a 3.7 V battery supply. Default solution with several supplies is impracticable w.r.t. ...complex cabling, PCB design and larger form factor. Thus we present a DC-DC which is robust regarding input voltage range and flexible regarding output voltage range. A bandgap-derived output voltage from 0.5 V to 0.8 V is selectable. The battery supply voltage is monitored as an additional safety feature for bio-medical applications. In combination with a neural recording system in 22 nm FDSOI, feasibility of scaling up to 1024 channels with an efficiency of up to 78.4 % is shown.
In neural implants and biohybrid research systems, the integration of electrode recording and stimulation front-ends with pre-processing circuitry promises a drastic increase in real-time ...capabilities 1,6. In our proposed neural recording system, constant sampling with a bandwidth of 9.8kHz yields 6.73 \mu \text{V} input-referred noise (IRN) at a power-per-channel of 0.34 \mu \text{W} for the time-continuous \Delta \Sigma -modulator, and 0.52 \mu \text{W} for the digital filters and spike detectors. We introduce dynamic current/bandwidth selection at the \Delta \Sigma and digital filter to reduce recording bandwidth at the absence of spikes (i.e. local field potentials). This is controlled by a two-level spike detection and adjusted by adaptive threshold estimation (ATE). Dynamic bandwidth selection reduces power by 53.7%, increasing the available channel count at a low heat dissipation. Adaptive back-gate voltage tuning (ABGVT) compensates for PVT variation in subthreshold circuits. This allows 1.8V input/output (IO) devices to operate at 0.4V supply voltage robustly. The proposed 64-channel neural recording system moreover includes a 16-channel adaptive compression engine (ACE) and an 8-channel on-chip current stimulator at 3.3V. The stimulator supports field-shaping approaches, promising increased selectivity in future research.
In neural implants and biohybrid research systems, the integration of electrode recording and stimulation front-ends with pre-processing circuitry promises a drastic increase in real-time ...capabilities 1,6. In our proposed neural recording system, constant sampling with a bandwidth of 9.8kHz yields 6.73μV input-referred noise (IRN) at a power-per-channel of 0.34μW for the time-continuous ΔΣ−modulator, and 0.52μW for the digital filters and spike detectors. We introduce dynamic current/bandwidth selection at the ΔΣ and digital filter to reduce recording bandwidth at the absence of spikes (i.e. local field potentials). This is controlled by a two-level spike detection and adjusted by adaptive threshold estimation (ATE). Dynamic bandwidth selection reduces power by 53.7%, increasing the available channel count at a low heat dissipation. Adaptive back-gate voltage tuning (ABGVT) compensates for PVT variation in subthreshold circuits. This allows 1.8V input/output (IO) devices to operate at 0.4V supply voltage robustly. The proposed 64-channel neural recording system moreover includes a 16-channel adaptive compression engine (ACE) and an 8-channel on-chip current stimulator at 3.3V. The stimulator supports field-shaping approaches, promising increased selectivity in future research.
