Nanoelectronic devices based on 2D materials are far from delivering their full theoretical performance potential due to the lack of scalable insulators. Amorphous oxides that work well in silicon ...technology have ill-defined interfaces with 2D materials and numerous defects, while 2D hexagonal boron nitride does not meet required dielectric specifications. The list of suitable alternative insulators is currently very limited. Thus, a radically different mindset with respect to suitable insulators for 2D technologies may be required. We review possible solution scenarios like the creation of clean interfaces, production of native oxides from 2D semiconductors and more intensive studies on crystalline insulators.
For ultra-scaled technology nodes at channel lengths below 12 nm, two-dimensional (2D) materials are a potential replacement for silicon since even atomically thin 2D semiconductors can maintain ...sizable mobilities and provide enhanced gate control in a stacked channel nanosheet transistor geometry. While theoretical projections and available experimental prototypes indicate great potential for 2D field effect transistors (FETs), several major challenges must be solved to realize CMOS logic circuits based on 2D materials at the wafer scale. This review discusses the most critical issues and benchmarks against the targets outlined for the 0.7 nm node in the International Roadmap for Devices and Systems scheduled for 2034. These issues are grouped into four areas; device scaling, the formation of low-resistive contacts to 2D semiconductors, gate stack design, and wafer-scale process integration. Here, we summarize recent developments in these areas and identify the most important future research questions which will have to be solved to allow for industrial adaptation of the 2D technology.
Abstract
Two-dimensional materials have been widely investigated to implement memristive devices for data storage or neuromorphic computing applications because of their ultra-scaled thicknesses and ...clean interfaces. For example, resistance switching in hexagonal boron nitride (h-BN) has been demonstrated. This mechanism is most of the time attributed to the movement of metallic ions. It has however also been reported when h-BN is contacted with two inert electrodes such as graphene or Pt. We suggest here that the switching mechanism of the latter devices, which has not yet been clearly established, relies on locals change of the electronic structure of h-BN as caused by atomic defects, e.g., multi-vacancies. This class of intrinsic h-BN defects can create electrically controllable interlayer bridges. We use a combination of hybrid density functional theory and the Non-equilibrium Green’s function formalism to show that a single interlayer bridge resulting from the presence of a trivacancy in a graphene/h-BN/graphene stack leads to a switching voltage of ~5 V and a high-to-low resistance ratio >100. Both values lie within the reported experimental range and thus confirm the likelihood that intrinsic defects play a key role in the resistance switching of h-BN in contact with inert electrodes.
Even though the hysteresis in the gate transfer characteristics of two-dimensional (2D) transistors is a frequently encountered phenomenon, the physics behind it are up to now only barely understood, ...let alone modeled. Here, we demonstrate that the hysteresis phenomenon can be captured accurately by a previously established non-radiative multiphonon model describing charge capture and emission events in the surrounding dielectrics. The charge transfer model is embedded into a drift-diffusion based TCAD simulation environment, which was adapted to 2D devices. Our modeling setup was validated against measurement data on a back-gated single-layer MoS 2 transistor with SiO 2 as a gate dielectric. We use the modeling approach to gain a thorough understanding of the hysteresis, which will help to control this problem in future devices.
Abstract Evidence of microscopic inhomogeneities of the side source/drain contacts in 300 mm wafer integrated MoS 2 field-effect transistors is presented. In particular, the presence of a limited ...number of low Schottky barrier spots through which channel carriers are predominantly injected is demonstrated by the dramatic current changes induced by individual charge traps located near the source contact. Two distinct types of “contact-impacting traps” are identified. Type-1 trap is adjacent to the contact interface and exchanges carriers with the metal. Its impact is only observable when the adjacent contact is the reverse-biased FET source and limits the channel current. Type-2 trap is located in the AlO x gate oxide interlayer, near the source contact, and exchanges carriers with the channel. Its capture/emission time constants exhibit both a gate and drain bias dependence due to the high sensitivity of the contact regions to the applied lateral and vertical fields. Unlike typical channel-impacting oxide traps, both types of reported defects affect the Schottky barrier height and width rather than the threshold voltage and result in giant random telegraph noise (RTN). These observations indicate that the contact quality and geometry play a fundamental role in the ultimate scaling of 2D FETs.
We propose double-gated n-type WSe 2 FETs with low leakage, low hysteresis top gate high-k dielectric stack. The top gate dielectric layer is deposited by HfO 2 ALD on an Al 2 O 3 seed layer obtained ...from the evaporation and oxidation by air exposure of a 1.5 nm Al layer. When operated under back gate control, the fabricated WSe 2 FETs behave as n-type enhancement transistors with ON/OFF current ratios exceeding 6 orders of magnitude and a ON current close to 1 μA/μm at a drain bias of 100 mV. An applied negative top gate bias determines a much steeper turn-on of the back gated transfer characteristic and a reduction of the observed hysteresis. Top gate devices behave as n-type depletion FETs, reaching a ION/IOFF ratio larger than 10 6 under positive bias applied to the back gate. The electron mobility, extracted using the Y-function method, was estimated to be 22.15 cm 2 V -1 s -1 under a drain bias of 1 mV. We characterize the hysteresis dynamics in our devices, demonstrating a substantial improvement with respect to comparable top gated MoS 2 FETs.
We report considerable improvement in the hysteresis and reliability of single-layer MoS 2 field-effect transistors (FETs) achieved by chemical vapor deposition (CVD) of MoS 2 and dielectric ...encapsulation. Our results show that a high-quality 15-nm thick Al 2 O 3 layer allows for an efficient protection of the devices from adsorbent-type trapping sites. Combined use of the CVD-grown MoS 2 as a channel and encapsulation simultaneously leads to at least an order of magnitude smaller hysteresis and up to two orders of magnitude lower long-term drifts of the transistor characteristics. Together with high on/off current ratios (~10 9 ) achieved in our devices, this presents a considerable advance in the technology of MoS 2 FETs. As such, we conclude that both CVD growth of MoS 2 and encapsulation present important technological steps toward reaching commercial quality standards of next-generation two-dimensional (2D) material technologies.
Within the last decade, considerable efforts have been devoted to fabricating transistors utilizing 2D semiconductors. Also, small circuits consisting of a few transistors have been demonstrated, ...including inverters, ring oscillators, and static random access memory cells. However, for industrial applications, both time‐zero and time‐dependent variability in the performance of the transistors appear critical. While time‐zero variability is primarily related to immature processing, time‐dependent drifts are dominated by charge trapping at defects located at the channel/insulator interface and in the insulator itself, which can substantially degrade the stability of circuits. At the current state of the art, 2D transistors typically exhibit a few orders of magnitude higher trap densities than silicon devices, which considerably increases their time‐dependent variability, resulting in stability and yield issues. Here, the stability of currently available 2D electronics is carefully evaluated using circuit simulations to determine the impact of transistor‐related issues on the overall circuit performance. The results suggest that while the performance parameters of transistors based on certain material combinations are already getting close to being competitive with Si technologies, a reduction in variability and defect densities is required. Overall, the criteria for parameter variability serve as guidance for evaluating the future development of 2D technologies.
2D field‐effect‐transistors (FETs) are affected by time‐dependent changes in their performance, which must be minimized for industrial‐scale applications. In this work, the stability of circuits based on 2D transistors is evaluated. The results suggest that the performance parameters of certain material combinations for 2D FETs are already close to Si technologies. Furthermore, parameter variability criteria are formulated to evaluate the future development of 2D technologies.
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