This paper proposes an efficient pipelined architecture of elliptic curve scalar multiplication (ECSM) over GF(2 m ). The architecture uses a bit-parallel finite field (FF) multiplier accumulator ...(MAC) based on the Karatsuba-Ofman algorithm. The Montgomery ladder algorithm is modified for better sharing of execution paths. The data path in the architecture is well designed, so that the critical path contains few extra logic primitives apart from the FF MAC. In order to find the optimal number of pipeline stages, scheduling schemes with different pipeline stages are proposed and the ideal placement of pipeline registers is thoroughly analyzed. We implement ECSM over the five binary fields recommended by the National Institute of Standard and Technology on Xilinx Virtex-4 and Virtex-5 field-programmable gate arrays. The three-stage pipelined architecture is shown to have the best performance, which achieves a scalar multiplication over GF(2163) in 6.1 μs using 7354 Slices on Virtex-4. Using Virtex-5, the scalar multiplication for m = 163, 233, 283, 409, and 571 can be achieved in 4.6, 7.9, 10.9, 19.4, and 36.5 μs, respectively, which are faster than previous results.
A photoelectrochemical sensing strategy for highly sensitive detection of thrombin was developed based on a layer-by-layer (LBL) assembly of functionalized graphene and CdSe nanoparticles.
In this brief, a non-least positive form (NLP) based modular multiplication method that combines Karatsuba and schoolbook multiplication is applied in Montgomery modular multiplication, which saves 2 ...base multiplications compared to Karatsuba-only designs and allows pipeline structure to make most use of the parallelism in large modular multiplications. Based on this method, 256-bit and 512-bit modular multipliers are constructed with 3-way and 4-way NLP multipliers on FPGA platform. Implemented on Virtex-6, the 256-bit design can perform a modular multiplication in 62.6 ns and only requires 3.5K LUTs and 24 DSPs, which exhibits low-latency and low-cost among previous works.
Toom-Cook multiplication is a theoretically more efficient multiplication algorithm than traditionally used Karatsuba and schoolbook multiplication but is rarely used in practical hardware designs ...due to its inherent exact divisions, which are time-consuming and difficult for parallel and serial acceleration. This brief proposes a method of division-free Toom-Cook multiplication based Montgomery modular multiplication, which makes it possible for Toom-Cook multiplication to be applied in practical and efficient hardware implementations. We also provide a hardware implementation of modular multipliers of 256 bits and 1024 bits with advantages on area-time-product over previous researches.
Cryptography based on ring learning with error (RLWE) problem has become increasingly popular due to its resistance against quantum analysis. The most time-consuming operation in RLWE cryptosystem is ...polynomial multiplication. This brief presents a novel polynomial multiplier based on Stockham fast Fourier transform (FFT) algorithm. We propose a multi-lane number theoretic transform (NTT) algorithm which can achieve n-degree polynomial multiplication in (nlgn)/d + 2n/d clock cycles with d lanes of butterfly units. In addition, we also customize a memory addressing strategy and a round constant managing scheme for the proposed multi-lane NTT algorithm. Based on our proposed algorithm, a high-speed polynomial multiplier is accomplished on FPGA platform. Implementation results on Spantan-6 FPGA show that our proposed algorithm can achieve a speed up factor of no less than 2.7 times compared with the state of art designs.
This brief proposes a novel hardware structure for large integer multiplication in fully homomorphic encryption. We propose a method based on negative wrapped convolution to avoid zero padding in ...Strassen's algorithm, which can cut down half of the Fourier transform length. In addition, we also optimize the ping-pong fast Fourier transform algorithm by doubling the transform throughput and generating the round constant on the fly. Based on our proposed method and optimized algorithm, we design and implement a 768 k-bit integer multiplier on Altera Stratix V field-programmable gate array (FPGA). Implementation results on FPGA show that our structure outperforms the current competitors in area efficiency.
In this paper, a high-speed elliptic curve cryptography (ECC) processor specialized for primes recommended by the National Institute of Standards and Technology (NIST) was constructed. Toom-Cook ...multiplication without division was proposed to implement modular multiplication for NIST primes. Compared with a traditional algorithm, the computation complexity was reduced from 16 base multiplications to 7 in 4-way Toom-Cook multiplication. Moreover, we introduced non-least-positive (NLP) form into our design, so that the carry chain in the large array accumulation was broken down, which greatly shortened the critical path and made parallel processing possible. In order to support NLP form and lazy reduction strategy, conventional fast reduction methods for NIST primes were also modified. In addition, pipeline technique at the level of point multiplication was used, so the latency of modular inverse can be covered. Implemented on the Xilinx Virtex-6 FPGA platform, the ECC processor can perform a point multiplication every 54 μs at the cost of 30.3k LUTs and 48 DSPs. Synthesized with 180nm CMOS technology, the speed achieves 43.7 μs with 466k gate counts. These experimental results show a significantly better performance per area than previous works.
Water repellent treatment is one of the effective means to improve the durability of concrete. This paper aims to investigate the water repellency of cement-based materials treated with silane-based ...water repellent agent under different exposure environments. Five different exposure conditions were applied in this experiment, namely, standard moist curing room, in-door laboratory atmosphere, pre-oven-dried condition, and out-door natural environment with or without shelter. Three different types of mortars with water-to-cement ratios of 0.4, 0.5 and 0.6 were prepared. And three different dosages (200, 400, 600 g/m2) of silane gel were utilized on the surface of specimens. The impregnation depth and water absorption after hydrophobic treatment have been measured. Results indicate that the initial moisture condition of mortar has a significant influence on the efficiency of surface silane impregnation. The depth of silane impregnation gradually decreases with the increase of initial moisture condition. The water repellency of surface impregnation of cement-based materials was well exhibited under the condition of about 50% relative humidity. It illustrated that the moisture within the cement-based materials affects the hydrolysis reaction process and the formation of hydrophobic membrane. Thus, the water repellency of cement-based materials greatly depends on the initial moisture content and the thickness of hydrophobic layer.
This brief proposes a double modulus number theoretical transform (NTT) method for million-bit integer multiplication in fully homomorphic encryption. In our method, each NTT point is processed ...simultaneously under two moduli, and the final result is generated through the Chinese reminder theorem. The employment of double modulus enlarges the permitted NTT sample size from 24 to 32 bits and thus improves the transform efficiency. Based on the proposed double modulus method, we accomplish a VLSI design of million-bit integer multiplier with the Schönhage-Strassen algorithm. Implementation results on Altera Stratix-V FPGA show that this brief is able to compute a product of two 1024k-bit integers every 4.9 ms at the cost of only 7.9k ALUTs and 3.6k registers, which is more area-efficient when compared with the current competitors.
A photoelectrochemical sensing strategy for highly sensitive detection of small molecules was developed based on the recognition interaction between aptamer and target molecule-ATP.
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