Direct ionization from low energy protons is shown to cause upsets in a 65-nm bulk CMOS SRAM, consistent with results reported for other deep submicron technologies. The experimental data are used to ...calibrate a Monte Carlo rate prediction model, which is used to evaluate the importance of this upset mechanism in typical space environments. For the ISS orbit and a geosynchronous (worst day) orbit, direct ionization from protons is a major contributor to the total error rate, but for a geosynchronous (solar min) orbit, the proton flux is too low to cause a significant number of events. The implications of these results for hardness assurance are discussed.
Experimental results are presented on single-bit-upsets (SBU) and multiple-bit-upsets (MBU) on a 45 nm SOI SRAM. The accelerated testing results show the SBU-per-bit cross section is relatively ...constant with technology scaling but the MBU cross section is increasing. The MBU data show the importance of acquiring and analyzing the data with respect to the location of the multiple-bit upsets since the relative location of the cells is important in determining which MBU upsets can be corrected with error correcting code (ECC) circuits. For the SOI SRAMs, a large MBU orientation effect is observed with most of the MBU events occurring along the same SRAM bit-line; allowing ECC circuits to correct most of these MBU events.
We present experimental evidence of single-event upsets in 28 and 45 nm CMOS SRAMs produced by single energetic electrons. Upsets are observed within 10% of nominal supply voltage for devices built ...in the 28 nm technology node. Simulation results provide supporting evidence that upsets are produced by energetic electrons generated by incident X-rays. The observed errors are shown not to be the result of "weak bits" or photocurrents resulting from the collective energy deposition from X-rays. Experimental results are consistent with the bias sensitivity of critical charge for direct ionization effects caused by low-energy protons and muons in these technologies. Monte Carlo simulations show that the contributions of electron-induced SEU to error rates in the GEO environment depend exponentially on critical charge.
Experimental results are presented on proton induced single-event-upsets (SEU) on a 65 nm silicon-on-insulator (SOI) SRAM. The low energy proton SEU results are very different for the 65 nm SRAM as ...compared with SRAMs fabricated in previous technology generations. Specifically, no upset threshold is observed as the proton energy is decreased down to 1 MeV; and a sharp rise in the upset cross-section is observed below 1 MeV. The increase below 1 MeV is attributed to upsets caused by direct ionization from the low energy protons. The implications of the low energy proton upsets are discussed for space applications of 65 nm SRAMs; and the implications for radiation assurance testing are also discussed.
We have compared the data retention of irradiated commercial NAND flash memories with that of unirradiated controls. For parts aged by baking at high temperature, there was a statistically ...significant difference between irradiated samples and unirradiated controls. For parts aged by repetitive Program/Erase (P/E) cycling, the effect of radiation was not statistically significant.
We have compared the endurance of irradiated commercial NAND flash memories with that of unirradiated controls. Radiation exposure has little or no effect on the endurance of flash memories. Results ...are discussed in light of the relevant models for electron and hole trapping.
The speed, tight timing requirements packaging and complicated error behavior of DDR2 and DDR3 SDRAMs pose significant challenges for single-event testing. Often, each new generation will require an ...expensive new tester with a state-of-the-art controller for the memory. We explore the trade-offs in the use of commercial FPGA based evaluation boards for radiation testing DDR2 and DDR3 SDRAMs. We evaluate the resulting data quality and discuss tester performance while also elucidating and comparing SEE susceptibilities in DDR2 and DDR3 SDRAMs.
The effects of device orientation on heavy ion-induced multiple-bit upset (MBU) in 65 nm SRAMs are examined. The MBU response is shown to depend on the orientation of the device during irradiation. ...The response depends on the direction of the incident ion to the n- and p-wells of the SRAM. The MBU response is simulated using Monte Carlo methods for a space environment. The probability is calculated for event size. Single-bit upsets in the space environment account for 90% of all events with exponentially decreasing probabilities of larger MBU events.
Heavy ion data for custom SRAMs fabricated in a 45-nm CMOS technology demonstrate the effects of N- and P-well contact densities on single-event latchup. Although scaling has improved latchup ...robustness, process-level immunity has not been achieved, indicating a continued need for latchup mitigation techniques. A simple, algorithmic approach for selecting N- and P-well contact densities is described that ensures latchup immunity while minimizing the area penalty.
We are presenting single-event effect testing results on a 22-nm fully depleted silicon-on-insulator test chip from GlobalFoundries. The 128-Mb static random access memory (SRAMs) were irradiated ...with heavy ions, and the results are compared to previous partially depleted technology generations (32 and 45 nm). The per-bit cross section is approximately an order of magnitude lower than the previous generations with a higher onset linear energy transfer (LET). No dependence on roll angle or input pattern was found. Tilt angle data follow the cosine law. Increasing the SRAM array supply voltage from the minimum tested 0.73 V to the maximum 1.08 V decreases SEE sensitivity by as much as 8%. Decreasing the p-well voltage from the nominal 0 V to the maximum −2 V increases the SEE cross section by as much as <inline-formula> <tex-math notation="LaTeX">2\times </tex-math></inline-formula>. The n-well voltage has little effect on the SEE sensitivity due to the specifics of the transistor layout in the SRAM. Changing both the n- and p-well voltages simultaneously results in identical results as when only the p-well voltage was changed.
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