This paper presents a 13 bit 50 MS/s fully differential ring amplifier based SAR-assisted pipeline ADC, implemented in 65 nm CMOS. We introduce a new fully differential ring amplifier, which solves ...the problems of single-ended ring amplifiers while maintaining the benefits of high gain, fast slew based charging and an almost rail-to-rail output swing. We implement a switched-capacitor (SC) inter-stage residue amplifier that uses this new fully differential ring amplifier to give accurate amplification without calibration. In addition, a new floated detect-and-skip (FDAS) capacitive DAC (CDAC) switching method reduces the switching energy and improves linearity of first-stage CDAC. With these techniques, the prototype ADC achieves measured SNDR, SNR, and SFDR of 70.9 dB (11.5b), 71.3 dB and 84.6 dB, respectively, with a Nyquist frequency input. The prototype achieves 13 bit linearity without calibration and consumes 1 mW. This measured performance is equivalent to Walden and Schreier FoMs of 6.9 fJ/conversion ·step and 174.9 dB, respectively.
This paper presents a time-interleaved (TI) SAR ADC which enables background timing skew calibration without a separate timing reference channel and enhances the conversion speed of each SAR channel. ...The proposed ADC incorporates a flash ADC operating at the full sampling rate of the TI ADC. The flash ADC output is multiplexed to resolve MSBs of the SAR channels. Because the full-speed flash ADC does not suffer from timing skew errors, the flash ADC output is also used as a timing reference to estimate the timing skew of the TI SAR ADCs. A prototype ADC is designed and fabricated in a 65 nm CMOS process. After background timing skew calibration, 51.4 dB SNDR, 59.1 dB SFDR, and ±1.0 LSB INL/DNL are achieved at 1 GS/s with a Nyquist rate input signal. The power consumption is 18.9 mW from a 1.0 V supply, which corresponds to 62.3 fJ/step FoM.
Closed-loop neuromodulation for the treatment of neurological disorders requires monitoring of the brain activity uninterruptedly even during neurostimulation. This article presents a bidirectional ...32-channel CMOS neural interface that can record neural activity during stimulation. Each channel consists of a dc-coupled <inline-formula> <tex-math notation="LaTeX">\Delta ^{2} \Sigma </tex-math></inline-formula>-modulated analog-to-digital converter (neural-ADC), which records slow potentials (< 0.1 Hz) while accommodating rail-to-rail dc offset using a spectrum-shaping front-end. This front-end equalizes the neural signal spectrum before signal quantization, which reduces the energy consumption and silicon area. Upon detection of a large artifact by an in-channel event-triggered digital block, the modulator feedback DAC tracks the artifact with step sizes incrementing in a radix-2 exponential form, preventing the neural-ADC from saturation. Upon tracking the artifact, the multi-bit DAC step size is reduced to zoom into the input neural signal at the highest recording resolution. The modulator's multi-bit DAC is reused in a time-shared fashion as a current-mode stimulator with no area overhead. The <inline-formula> <tex-math notation="LaTeX">\Delta ^{2} \Sigma </tex-math></inline-formula>-ADC consumes 1.7 <inline-formula> <tex-math notation="LaTeX">\mu \text{W} </tex-math></inline-formula> from 0.6-V/1.2-V digital/analog supplies and time-shares the modulator's feedback DAC as the multi-bit current-mode stimulator operating at 3.3 V. The ADC occupies a silicon area of 0.023 mm 2 in the 130-nm CMOS and achieves a signal-to-noise-and-distortion ratio (SNDR) of 70 dB over the 500-Hz bandwidth and an equivalent noise efficiency factor (NEF) of 2.86 without a stand-alone front-end amplifier. The 32-channel bidirectionally interfacing prototype is validated in the in vivo whole brain of a rodent.
This article presents a power efficient and process, voltage, and temperature (PVT) robust pipelined successive approximation register (SAR) analog-to-digital converter (ADC) that quantizes signals ...in both voltage and time domains. In this work, a low-power SAR ADC is adopted as the coarse quantizer, while a ring-configured time-to-digital converter (TDC) is utilized in the fine quantizer to improve the linearity and power efficiency. In addition, the ring TDC also participates in the voltage-to-time conversion to guarantee that one-lap delay in the ring TDC is aligned with the least quantization step in the voltage domain. As a result, an auto-scale alignment between voltage and time domains is promised regardless of PVT variations. The ADC prototype IC was fabricated in a 22-nm CMOS technology. When measured at 260 MS/s, the ADC achieves 60.5-dB signal-to-noise and distortion ratio (SNDR) and 77-dB spurious-free dynamic range (SFDR) with a Nyquist input, while consuming 0.97 mW from a 0.8-V power supply. The calculated Walden and Schreier figures-of-merit (FoMs) are 4.27 fJ/conversion step and 171.8 dB, respectively.
A 12 bit 100 MS/s SAR-Assisted Digital-Slope ADC Liu, Chun-Cheng; Huang, Mu-Chen; Tu, Yu-Hsuan
IEEE journal of solid-state circuits,
2016-Dec., 2016-12-00, Letnik:
51, Številka:
12
Journal Article
Recenzirano
This paper presents an energy-efficient successive approximation register (SAR)-assisted digital-slope analog-todigital converter (ADC) architecture for high-resolution applications. The proposed ...hybrid ADC combines a low-noise fine digital-slope ADC with a low-power coarse SAR ADC. The coarse SAR ADC rapidly approximates the input signal and produces a small residue signal for the succeeding fine ADC. The fine digital-slope ADC linearly approaches the small residue signal. A prototype was fabricated in 1P8M 28 nm CMOS technology. At 100 MS/s, the ADC achieves a signal-to-noise-and-distortion ratio of 64.43 dB and a spurious free dynamic range of 75.42 dB at the Nyquist input frequency while consuming 0.35 mW from a 0.9 V supply. The resultant Walden and Schreier figures of merit are 2.6 fJ/conversion-step and 176.0 dB, respectively. The ADC occupies an active area of 66 μm × 71 μm.
This article presents a continuous-time zoom analog to digital converter (ADC) for audio applications. It employs a high-speed asynchronous SAR ADC that dynamically updates the references of a ...continuous-time delta-sigma modulator (CTDSM). Compared to previous switched-capacitor (SC) zoom ADCs, its input impedance is essentially resistive, which relaxes the power dissipation of its reference and input buffers. Fabricated in a 160-nm CMOS process, the ADC occupies 0.27 mm 2 and achieves 108.1-dB peak SNR, 106.4-dB peak signal to noise and distortion ratio (SNDR), and 108.5-dB dynamic range in a 20-kHz bandwidth while consuming 618 <inline-formula> <tex-math notation="LaTeX">\mu \text{W} </tex-math></inline-formula>. This results in a Schreier figure of merit (FoM) of 183.6 dB.
This article describes a discrete-time zoom analog-to-digital converter (ADC) intended for audio applications. It uses a coarse 5-bit SAR ADC in tandem with a fine third-order delta-sigma modulator ...(<inline-formula> <tex-math notation="LaTeX">\Delta \Sigma \text{M} </tex-math></inline-formula>) to efficiently obtain a high dynamic range. To minimize its over-sampling ratio (OSR) and, thus, its digital power consumption, the modulator employs a 2-bit quantizer and a loop filter notch. In addition, an extra feed-forward path minimizes the leakage of the SAR ADC's quantization noise into the audio band. The prototype ADC occupies 0.27 mm 2 in a 0.16-<inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula> technology. It achieves 109.8-dB DR, 106.5-dB SNDR, and 107.5-dB SNR in a 20-kHz bandwidth while dissipating 440 <inline-formula> <tex-math notation="LaTeX">\mu \text{W} </tex-math></inline-formula>. It also achieves state-of-the-art energy efficiency, as demonstrated by a Schreier FoM of 186.4 dB and an SNDR FoM of 183.6 dB.
Low-noise ring amplifiers required for high-precision analog-digital converters (ADCs) greater than 16 b remain unexplored. This article demonstrates a two-step successive approximation (SAR) ADC ...achieving 91-dB signal-to-noise-and-distortion-ratio (SNDR) with 6-V differential input resulting in a low-frequency Schreier-figure-of-merit (FOMS,lf ) of 179.8 dB at 15 MS/s. The state-of-the-art performance is enabled by the ring-amplifier design that enables low noise during amplification and robust control of the transient dynamics. The ADC also features an on-chip residue amplifier (RA) settling characterization using the backend SAR ADC. The ADC is fabricated in a 180-nm CMOS process and occupies an active area of 1.82 mm 2 .
This paper reviews and discusses a brief history of Nyquist ADCs. Bipolar flash ADCs for early development stage of HDTV and digital oscilloscopes, a Bi-CMOS two-step flash ADC using resistive ...interpolation for home HDTV receivers, a CMOS two-step flash ADC using capacitive interpolation for handy camcorders, pipelined ADCs using CMOS operational amplifiers, CMOS flash ADCs using dynamic comparator and digital offset compensation, SAR ADCs using low noise dynamic comparators and MOM capacitors, and hybrid ADCs are reviewed.
This paper proposes an adaptive all-digital background compensation of timing skew mismatches in time-interleaved analog-to-digital converters (TI-ADCs). The proposed approach uses the orthogonality ...between the desired component representing ideal samples of the TI-ADC input signal and the timing skew mismatch errors. Our technique is the first attempt to use a source separation mechanism to recover the desired component in the digital output of TI-ADC. A finite impulse response (FIR) filter implementing the Hilbert transform and two separate adaptive FIR (A-FIR) filters are exploited to implement this recovery process. The proposed technique works at frequencies close to the full admissible Nyquist frequency range, and its operation does not depend on the number of sub-ADCs (SADCs). This method operates without any extra SADC. The main cost introduced by the proposed compensation technique is the requirement of two adjustable FIR filters. This cost is proportional to the number of taps in these FIR filters that can be optimized according to the specific application. This technique is validated through various behavioral simulations and a field-programmable-gate-array (FPGA) implementation. With the proposed method, the signal-to-noise and distortion ratio (SNDR) is enhanced from 23.06 dB to more than 66.82 dB in a 12-bit TI-ADC when the standard deviation of timing skew mismatches is 10% of the TI-ADC's sampling interval.
