Three-Phase PLLs: A Review of Recent Advances Golestan, Saeed; Guerrero, Josep M.; Vasquez, Juan C.
IEEE transactions on power electronics,
2017-March, 2017-3-00, 20170301, Letnik:
32, Številka:
3
Journal Article
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A phase-locked loop (PLL) is a nonlinear negative-feedback control system that synchronizes its output in frequency as well as in phase with its input. PLLs are now widely used for the ...synchronization of power-electronics-based converters and also for monitoring and control purposes in different engineering fields. In recent years, there have been many attempts to design more advanced PLLs for three-phase applications. The aim of this paper is to provide overviews of these attempts, which can be very useful for engineers and academic researchers.
•The effect of the PLL and PLL less based control techniques on the performance of grid connected inverter is shown.•The effect of zg on the converter performance is highly effected with VCC DQ ...control compared to NPVC control.•The phase lag due to increased zg on VCC DQ control is more compared to NPVC control.•This NPVC control showed robust performance under transient, steady state, voltage sag and swell conditions of the Grid voltage variations.•With only L filter, the mathematical and computation burden are reduced with improved THD%.
In the micro-grids, all the Distributed Power Generation Systems (DPGS) and loads are interconnected across the Point of Common Coupling (PCC). The stability and harmonics of the grid connected inverters are significantly impacted by uncertainties in the renewable energy sources based DPGS. The performance of these grid connected inverters across the PCC depends on the Phase-Locked Loop (PLL) used to track the grid angle and power control structures used to control the power fed to grid. These power control structures can be either PLL based or PLL less systems. The PLL based Vector Current Control Direct Quadrature (VCC DQ) control and PLL less Non-PLL Vector Control (NPVC) techniques are compared along with their controller design and bode plots. Also, the small signal models of grid connected inverter with PLL are presented from which the converter impedance is derived to show the effect of PLL on the system using bode plots. The impact of the PLL based and PLL less control techniques on the grid connected inverter are presented with analytical equations along with simulation and hardware results. A 6 kW grid connected inverter simulation model and 150 W hardware prototype is developed using TI F28379D processor to compare the performance of both with and without PLL control techniques.
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The three-phase synchronous reference frame phase-locked loop (3-SRF-PLL) is widely used in three-phase power electronics and power system applications thanks to its desirable performance and its ...simple yet robust structure. Inspired from the 3-SRF-PLL and due to the increasing interest in single-phase applications, multiple single-phase SRF-PLL (1-SRF-PLL) versions have also been proposed in the recent years. This paper presents a unifying approach to the understanding and analysis of the 1 -SRF-PLLs. This paper integrates several 1 -SRF-PLLs having apparently different structures into a single structure. The approach is much useful in understanding various PLLs and also in facilitating further developments in this field.
Despite the ability of type-3 phase-locked loop (PLL) to provide zero steady-state error when a three-phase voltage experiences frequency ramp change, its major drawback is slow dynamic performance ...and instability during voltage sag condition. In this paper, by obtaining the linearised model of PLL, instability associated with the presence of voltage amplitude within the PLL control loop is illustrated. Furthermore, analysis of two common techniques employed in improving PLL stability (high phase margin design and use of phase-lead compensator) is presented and their inapplicability to three-phase type-3 PLL is revealed. Thus, to address the said problems, a gain compensation technique is proposed in this paper. In the proposed approach, the PLL loop gain is adjusted by inserting a DC gain within the PLL control loop when the frequency of supply voltage deviates from its nominal value. The inserted DC gain compensates for reduction in voltage amplitude within the PLL control loop, thus, enhancing PLL's stability especially during voltage sags. Also, the gain increases PLL's bandwidth thereby improving its estimation speed. Effectiveness of the proposed solution is confirmed through experimental studies and it is compared with five existing type-3 PLL schemes and a type-2 PLL.
In this paper, the enhanced phase-locked loop (EPLL) is modified to achieve a linear time invariant (LTI) and a pseudolinear (PL) EPLL called the LTI-EPLL and the PL-EPLL, respectively. The ...modification is based on using the estimated amplitude to make the EPLL operation independent from the input signal magnitude. The LTI-EPLL is input-output LTI, and its input-output relationship is represented by a transfer function, a representation that has not been possible for any other type of existing PLL structures. Having a transfer function representation is very useful for design and analysis purposes. The PL-EPLL introduces frequency adaptivity into the LTI-EPLL and is no longer LTI, but its performance is still independent from the input signal magnitude. The transfer function approach also facilitates the development and design of various EPLL extensions to estimate and reject the dc component and the harmonics as well as the extension with controlled attenuation of wideband noises. These topics are discussed in this paper. The presentation is focused on single-phase EPLL, but extension to three-phase PLLs is also briefly presented.
We present an analog subsampling PLL based on a digital-to-time converter (DTC), which operates with almost no performance gap (176/198 fs RMS jitter) between the integer and the worst case ...fractional operation, achieving -246.6 dB FOM in the worst case fractional mode. The PLL is capable of two-point, 10 Mbit/s GMSK modulation with -40.5 dB EVM around a 10.24 GHz fractional carrier. The analog nonidealities-DTC gain, DTC nonlinearity, modulating VCO bank gain, and nonlinearity-are calibrated in the background while the system operates normally. This results in ~15 dB fractional spur improvement (from -41 dBc to -56.5 dBc) during synthesis and ~15 dB EVM improvement (from -25 dB to -40.5 dB) during modulation. The paper provides an overview of the mechanisms that contribute to performance degradation in DTC-based PLL/phase modulators and presents ways to mitigate them. We demonstrate state-of-the-art performance in nanoscale CMOS for fractional-N synthesis and phase modulation.
The phase-locked loop (PLL) is the main controller element for the fast and accurate synchronisation and operation of grid-connected renewable energy systems (RESs). It is used to extract the grid ...voltage information such as the phase angle, the frequency and amplitude. Subsequently, this information is used in the control system of the grid-side converter of the RES. The performance of the PLL is critical under abnormal grid conditions such as in the event of balanced and/or unbalanced faults, frequency and phase variations, the presence of harmonics, interharmonics and DC offset. This study sets out with a benchmarking study of the four latest state-of-the-art PLLs. The PLLs compared are the decoupled dual synchronous reference frame PLL, the decoupling network designed in αβ-frame PLL, the enhanced pre-filtering moving average filter type-2 PLL and the harmonic–interharmonic DC-offset PLL. The PLLs are analysed and compared based on their performance, their dynamic response and their computational complexity. The benchmarking concludes with a PLL selection guide depending on the application and other system constraints. Experiments and simulation results are presented to compare and analyse the performance of the selected PLLs.
This article presents approaches for efficient modeling and systematic design of enhanced phase-locked loop (ePLL) structures. While different ePLL structures have found a wide acceptance for various ...applications, their modeling and design aspects have not been fully and systematically reported in the existing literature. This article fills this gap by presenting an effective modeling approach for both the single- and three-phase ePLLs. The models are derived with a view to minimize the number of parameters to be adjusted to simplify the design. The models are then used to develop systematic design algorithms for their parameters. As an example, application of the ePLL in a grid-connected inverter is formulated and studied through simulation and experimental results. The design and simulation files are made available.
In three-phase power and energy applications, the synchronous reference frame phase-locked loop (SRF-PLL) is a popular tool for synchronization purposes. The SRF-PLL can be easily and effectively ...customized for different scenarios by changing its loop filter. Recently, some supposedly different PLLs using the steady-state linear Kalman filter have been developed. The main aim of this letter is to analyze these PLLs. It is demonstrated that they are actually equivalent to some well-known SRF-PLL structures and, therefore, provide no advantage compared to them.
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