Differing from synchronous generators, there are lack of physical laws governing the synchronization dynamics of voltage-source converters (VSCs). The widely used phase-locked loop (PLL) plays a ...critical role in maintaining the synchronism of current-controlled VSCs, whose dynamics are highly affected by the power exchange between VSCs and the grid. This article presents a design-oriented analysis on the transient stability of PLL-synchronized VSCs, i.e., the synchronization stability of VSCs under large disturbances, by employing the phase portrait approach. Insights into the stabilizing effects of the first- and second-order PLLs are provided with the quantitative analysis. It is revealed that simply increasing the damping ratio of the second-order PLL may fail to stabilize VSCs during severe grid faults, whereas the first-order PLL can always guarantee the transient stability of VSCs when equilibrium operation points exist. An adaptive PLL that switches between the second-order and the first-order PLL during the fault-occurring/-clearing transient is proposed for preserving both the transient stability and the phase-tracking accuracy. Time-domain simulations and experimental tests, considering both the grid fault and the fault recovery, are performed, and the obtained results validate the theoretical findings.
For grid-following inverters, an accurate grid impedance estimation (GIE) enables many beneficial applications. Conventional active GIE methods, such as the PQ variation method, intentionally ...introduce power disturbances around the system's steady-state operating point. However, it might bring undesired reactive power into the grid and its accuracy can be influenced by phase-lock loop (PLL) phase angle variations. To address these challenges, this letter proposes a noninvasive GIE method, which utilizes PLL's inherent operating characteristics. It only requires a single steady-state operating point transition that naturally occurs during the system's normal operation, eliminating the need to inject deliberate PQ disturbances. In addition, by considering PLL phase angle variations, this method also ensures accurate estimation results across diverse conditions. Experimental verifications are provided, which demonstrate the effectiveness and accuracy of the proposed method.
In this article, we present a low-power digital phase-locked loop (PLL)-based phase modulator targeting low error vector magnitude (EVM). We introduce a new non-uniform clock compensation (NUCC) ...scheme to tackle an EVM degradation resulting from the beneficial use of a time-varying sampling clock that is re-timed to the phase-modulated carrier. We also employ a phase-domain digital predistortion (DPD) to combat the intrinsic non-linearity of an LC-type digitally controlled oscillator (DCO), thus avoiding the complications of frequency-dependent calibrations. The prototype, implemented in 40-nm CMOS, modulates the carrier in the range of 2.7-3.9 GHz from a 40-MHz reference. The measured EVM is <inline-formula> <tex-math notation="LaTeX">-</tex-math> </inline-formula>47 dB for a 60-Mb/s 64-PSK modulation under the case that the phase-modulated output is frequency-divided by <inline-formula> <tex-math notation="LaTeX">K=8</tex-math> </inline-formula>, i.e., when the DCO exhibits the most significant non-linearity due to the large fractional FM bandwidth. When <inline-formula> <tex-math notation="LaTeX">K=8</tex-math> </inline-formula> or 4, the measured EVM remains below <inline-formula> <tex-math notation="LaTeX">-</tex-math> </inline-formula>43 dB across the carrier-frequency tuning range and without re-calibrating the DCO non-linearity.
This study investigates the stability of multiple three-phase converters connected to weak grids. It has been derived a flexible modelling regarding the number of converter and type of collector ...system. The both eigenvalues and impedance based methods are applied to the stability analysis. The eigenvalues method is used to give guidelines on the choice of the phase-looked loop (PLL) gains. To improve the stability margins, the increase in the PLL damping ratio is proposed. Moreover, it is used to investigate the PLL interaction with converter current and DC bus voltage controllers. The impedance based method extends the stability analysis to multiple three-phase converters. In addition, it has been used to show the effects of converter current and DC bus voltage controllers parameters on the stability margins. Finally, in order to validate the theoretical analysis, time-domain results with hardware-in-the-loop are given, showing a strong correlation with the theoretical analysis in the frequency domain.
All-digital PLLs (ADPLLs) based on a ring-oscillator (RO) provide very fast settling, but they suffer from quantization noise due to discrete tuning of their digitally controlled oscillator (DCO). ...Although RO charge-pump PLLs (CP-PLLs) do not exhibit quantization noise thanks to their continuous VCO tuning, they are quite slow and require huge VCO gain to cover frequency drift due to temperature variations. Further, in CP-PLLs, the reset pulse of phase detector (PD) must be wide for proper PLL functioning, but this sets a lower limit on reference spurs. We propose a hybrid-PLL in a 7-nm FinFET CMOS that combines the best advantages of ADPLL and CP-PLL. We introduce periodical phase realignment by the reference clock, and ultrashort pulse for resetting the PD. The hybrid PLL covers 0.2-4 GHz and settles in 0.6 us. It emits low −52 dB reference spurs in the conventional mode, and 1.05 ps and 0.62 ps integrated jitter in the conventional and realignment modes, respectively.
In this paper, a small-signal model of voltage source converter (VSC) is developed to investigate the stability of dc-link voltage control. This model contributes to representing the dc-link voltage ...dynamics characteristics of VSC integrated to weak grid. Effects of grid strength, operating point, and control loops' interactions on the performance of VSC are taken into consideration. Based on the proposed small-signal model, eigenvalue analysis is employed to study the stability of dc-link voltage control with varying operating conditions. Analysis results show that control loops' interactions introduce a partial positive feedback to the dc-link voltage control in weak grid. Furthermore, the effect of control loops' interactions on dc-link voltage control stability reaches largest when the bandwidth of the phase-locked loop is close to that of the dc-link voltage control. Time-domain simulations and experiments were conducted to validate the analysis.
This article presents a low jitter, low power, low reference spur LC oscillator-based reference oversampling digital phase locked loop (OSPLL). The proposed reference oversampling architecture ...simultaneously offers a low in-band phase noise, a wide-bandwidth, and a low spur. In addition, this article proposes an LC digitally controlled oscillator (DCO) for the proposed OSPLL to achieve a fast frequency update and fine frequency resolution, while its varactor switching timing is set optimally for low jitter using the proposed DCO tuning pulse timing control scheme. The proposed OSPLL was fabricated in a 28-nm CMOS process. The integrated rms jitter of the PLL was measured at 67.1 fs for an output frequency of 4 GHz. The in-band phase noise of the PLL was −129.2 and −132.5 dBc/Hz at 1- and 5-MHz offset frequencies. The measured reference spur of the PLL was −78.1 dBc. Total PLL power consumption was 5.2 mW, resulting in −256.3-dB PLL jitter-power FoM, while occupying 0.17-mm 2 area.
In this work, a new subsampling PLL is presented which samples the reference signal by the oscillator’s phase and then again by the divided oscillator phase. The operation is robust due to the action ...of a frequency divider in the loop. Fractional synthesis can also be easily implemented by modifying the loop containing the frequency divider using a ΔΣ modulator. Post-layout simulations are performed in CMOS 90 nm technology with a 1 GHz ring oscillator. Peak-to-peak jitter over 1000 cycles of the free running ring oscillator is 87 ps. It is reduced to 28 ps through the action of the proposed architecture.
•In-band phase noise due to PFD-CP is not present.•Robust locking to correct frequency of operation.•Fractional synthesis can be easily performed (no multiphasing required).
T-cell prolymphocytic leukemia (T-PLL) is an aggressive and rare T-cell malignancy with limited data reporting patient outcomes. Allogeneic transplant (allo-HCT) is the only option for cure.
We aim ...to report the treatment patterns and outcomes of T-PLL patients after allo-HCT from two centers in the United States.
We conducted a retrospective analysis of patients diagnosed with T-PLL who underwent allo-HCT between 2002-2022 at Dana Farber Cancer Institute and Massachusetts General Hospital. Time-to-event endpoints are estimated using the Kaplan-Meier method with 95% confidence intervals calculated using Greenwood's method to estimate variance.
Thirty-five patients were identified with a median age of 61 (range 41-77). The Karnofsky performance status was >90 for 49% of the patients (range 70-100%). The median number of transplants was 1 (range 1-2). Frontline therapies included: alemtuzumab (74%), fludarabine (11%), pentostatin (3%), and unknown (11%). The majority of patients (66%) received an unrelated donor allo-HCT. The most used conditioning regimen was busulfan and fludarabine (66% of patients). The most common GVHD regimen in 31% of the patients was methotrexate, sirolimus, and tacrolimus. The median follow-up was 60.8 months. Of the patients with graft versus host disease, 46% had acute GVHD (aGVHD), while 37% had chronic GVHD (cGVHD). Of the patients with aGVHD, 56% had grade 2, and 19% had grade 3. There were no grade 4 events. The patients who experienced cGVHD mostly had mild symptoms (69%). There was no severe cGVHD. The median time to max grade was 3.4 months for aGCVD and 12.7 months for cGVHD. The median overall and progression-free survival were 24.0 and 21.1 months, respectively. The most common causes of death were disease progression (40%) and infections (11%). At 72 months, the probability of non-relapse mortality in the patients with vs without GVHD was 0.44 (0.18-0.71) vs 0.7 (0.3-1.11), and the transplant-related mortality (TRM) was 0.19 (0.02-0.37) vs 0.08 (0-0.23). This was not statistically significant.
The outcomes of T-PLL patients remain dismal despite allo-HCT, with relapse still being the most common cause of treatment failure. Novel therapies are needed for this rare and aggressive disease.
A fractional-N sub-sampling PLL architecture based on pipelined phase-interpolator and Digital-to-Time-Converter (DTC) is presented in this paper. The combination of pipelined phase-interpolator and ...DTC enables efficient design of the multi-phase generation mechanism required for the fractional operation. This technique can be used for designing a fractional-N PLL with low in-band phase noise and low spurious tones with low power consumption. The short-current-free pipelined phase-interpolator used in this work is capable of achieving high-linearity with low-power while minimizing the intrinsic jitter. A number of other circuit techniques and layout techniques are also employed in this design for ensuring high-performance operation with minimal chip area and power consumption. The proposed fractional-N PLL is implemented in standard 65 nm CMOS technology. The PLL has an operating range of 600 MHz from 4.34 GHz to 4.94 GHz. In fractional-N mode, the proposed PLL achieves -249.5 dB FoM and less than -59 dBc fractional spurs.
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