The demand for multi-band, low-power, and low-noise frequency synthesizers is growing rapidly due to increasing battery-operated Internet-of-Things (IoT) devices and high-speed communication systems. ...This paper proposes a low-power and dual-band sub-sampling phase-locked loop (SSPLL) with a low jitter requirement that uses a current reuse LC voltage control oscillator (LC-VCO). The proposed SSPLL can be configured at 2.4 GHz and 5 GHz frequencies by setting the frequency selection bits in the LC-VCO. The LC-VCO uses a supply-switching technique to minimize the power consumption of the design. The dual-band (2.4/5 GHz) frequencies are generated using a shared LC-tank, which saves around 46% of the LC-VCO core area. The proposed SSPLL is designed and simulated in a 65-nm industrial process node. The rigorous stability analysis and the modelling of the proposed SSPLL are performed, which shows the proposed SSPLL is stable at both 2.4 GHz and 5 GHz frequencies. To reduce the power consumption of the proposed SSPLL, the LC-VCO operates at a supply voltage of 0.9-V, while the rest of the blocks in the SSPLL work at a 1.2-V power supply. The parasitic extracted (PEX) netlist simulations of the proposed SSPLL architecture can produce 2.4 GHz and 5 GHz frequencies with a power consumption of 3.91 mW and 4.02 mW, respectively. The proposed SSPLL design achieves the rms jitter of 89.74 fs and 84.45 fs for 2.4 GHz and 5 GHz frequency modes, respectively, in the 10 kHz-100 MHz integration bandwidth. The jitter-power figure of merit (FOM) of the proposed SSPLL architecture is found to be −255.02 dB and −255.42 dB for 2.4 GHz and 5 GHz frequency operation, respectively. The total area of the layout of the proposed design is 0.253 mm 2 .
This article presents a wideband phase-locked loop (PLL) with a novel frequency acquisition loop for a wide locking range and wide bandwidth in 130 nm SiGe BiCMOS technology. The PLL contains two ...channels that work in parallel for the frequency acquisition and phase locking to form an analog phase frequency detector (PFD). The proposed frequency acquisition loop enables a fast frequency correction with a wide pull in range and accommodates frequency acquisition when a significant frequency difference is presented. The designed PLL provides the bandwidth of 55 MHz, a phase margin (PM) of 81.5°, and offers a wide frequency acquisition of 4.1 GHz. The proposed architecture allows simultaneous carrier synchronization and data de-modulations at front-end. The PLL has a measured phase noise of −124 dBc/Hz@1 MHz and the root mean square (rms) jitter integrated from 100 Hz to 1 GHz of 62.4 fs.
In many grid synchronization systems (GSSs), amplitude and phase estimation loops are dynamically coupled. It means that a change in the input voltage amplitude may result in spurious phase/frequency ...transients in the GSS output and vice versa. This article aims to explain the reason behind this coupling and present some guidelines to mitigate it. Several case studies are provided, and numerical and experimental results are presented to make all this more clear.
Conventional SOGI-PLL, designed for DC offset (DCO) free measurements, experiences significant accuracy degradation in the presence of DCO. To tackle this issue, literature offers various solutions, ...including low- and high-order methods. This letter focuses onlow-order methods due to their computational and implementation simplicity. It has been modeled, tuned, and systematically analyzed for the first time using a constructive approach, three key low-order DCO rejection methods: ESOGI, TOGI, and LSOGI. Results indicate that LSOGI and TOGI share similar time and frequency-domain characteristics, while ESOGI prioritizes fast dynamic response over steady-state accuracy. Therefore, careful consideration is necessary when choosing DCO rejection methods based on specific application requirements. The results presented here offer explicit guidance in this context
The inverter nonlinearity and the flux spatial harmonics will lead to noticeable (6κ±1) harmonics in the observed back electromotive force (EMF), causing (6κ) pulsations in the rotor position ...estimation error and deteriorating the performance of sensorless interior permanent magnet synchronous motor (IPMSM) drives. To improve the sensorless IPMSM control accuracy, a multiple discrete adaptive filter (MDAF) embedded between sliding mode observer (SMO) and normalized quadrature phase-locked loop (PLL) is adopted to solve the above problem in this paper. The MDAF consists of a fundamental extraction block and a harmonic cancellation block. Harmonic cancellation works similarly to fundamental extraction, simply by removing the dominant 5th and 7th harmonics from the distorted back-EMF in a frequency multiplicative manner. The proposed algorithm is designed directly in the discrete domain, avoiding the complex discretization process. The open-loop amplitude-frequency characteristic curves show that the method is able to achieve infinite gain exactly at the expected frequency, thus allowing closed-loop zero steady-state error tracking of the back-EMF and providing higher precision for harmonic estimation. The excellent performance of the suggested method is validated based on a 1.5kW sensorless IPMSM control system.
A fully integrated sub-terahertz (sub-THz) frequency synthesizer is proposed cascading a radio frequency subsampling phase-locked loop (SS-PLL) with millimeter-wave injection-locked frequency ...multipliers (ILFMs) and a sub-THz mixer for frequency extension. Enhanced third-harmonic and fourth-harmonic-extraction techniques are proposed for the ILFMs with different multiplication ratios. In addition, a frequency-tracking loop (FTL) with automatic frequency and amplitude calibration is embedded for the ILFMs. Finally, a distributed bias technique is employed to improve the linearity of the wideband magnetic-tuning sub-THz oscillator. Designed in a 65-nm CMOS process, the proposed prototype achieves an ultra-wide frequency tuning range from 61.2 to 100.8, 122.4 to 136.8, and 198.5 to 273.6 GHz with a phase noise at 1-MHz offset from −79.3 to −95.4 dBc/Hz and an integrated jitter from 124 to 159 fs over the tuning range. The synthesizer occupies a core area of 0.58 mm 2 and measures an output power of −11 dBm at 211.4 GHz with 49.5 mW, corresponding to a dc-to-radio frequency (RF) efficiency of 0.16%, an FoM from −171.4 to −177.7 dBc/Hz, and <inline-formula> <tex-math notation="LaTeX">{\mathrm {FoM}}_{T} </tex-math></inline-formula> from −177 to −190.5 dBc/Hz.
When unbalanced faults such as single-phase voltage drop occur in the power grid, VSC-HVDC will fail or become unstable due to sudden changes in amplitude, phase, frequency, etc. of the power grid ...voltage. Therefore, the role of PLL in a non-ideal power grid is particularly important, but often PLL needs to make a compromise between dynamic response and system stability. Therefore, this paper proposes a free-PLL control strategy under non ideal power grid. First, according to the power transmission model of VSC-HVDC under power grid imbalance, the control command required by the inverter is given, which is determined in the environment free-PLL. Therefore, PLL is not required to retrace the phase of the grid voltage. In addition, in order to overcome the impact of the sudden change of power grid frequency on the free-PLL strategy, a frequency locking strategy is proposed in the free-PLL environment, the response time is about 1 grid cycle. Finally, in order to verify the effectiveness and correctness of the proposed strategy, the VSC-HVDC system’s active power transmission stability is guaranteed when the grid voltage encounters different degrees of single-phase sags.
This paper describes all-digital enhancements for digital fractional-<inline-formula> <tex-math notation="LaTeX">{N} </tex-math></inline-formula> phase-locked loops (PLLs) based on delta-sigma ...(<inline-formula> <tex-math notation="LaTeX">\Delta \Sigma </tex-math></inline-formula>) frequency-to-digital converters (FDCs). The enhancements include an improved dual-mode ring oscillator (DMRO)-based <inline-formula> <tex-math notation="LaTeX">\Delta \Sigma </tex-math></inline-formula> FDC architecture and a digital background calibration technique that compensates for the <inline-formula> <tex-math notation="LaTeX">\Delta \Sigma </tex-math></inline-formula> FDC's forward path gain error. The improved <inline-formula> <tex-math notation="LaTeX">\Delta \Sigma </tex-math></inline-formula> FDC has significantly relaxed timing constraints and a <inline-formula> <tex-math notation="LaTeX">3\times </tex-math></inline-formula> smaller phase-frequency detector output pulse-width span relative to the prior art, which make it simpler to implement and amenable to higher-frequency reference signals. The calibration technique compensates for non-ideal DMRO frequencies in the digital domain. It eliminates the need to tune the DMRO instantaneous frequencies as a function of the PLL output frequency, thereby simplifying the DMRO implementation, and it also improves the phase noise performance of PLLs with high loop bandwidths.
Phase-locked loop (PLL) is essential for the grid-connected inverter to ensure grid synchronization. Since the PLL introduces an negative-resistive admittance to be in parallel with the original ...inverter output admittance, it poses an instability risk for the grid-connected inverter under weak grid. The system stability can be evaluated by the return ratio matrix, which is the ratio of the inverter output admittance to the grid admittance. Due to the non-singular and non-diagonal properties of this matrix, its eigenvalues are irrational functions, leading to inconvenience of stability analysis and PLL parameters design. To address this issue, this paper reconstructs the return ratio matrix to make it singular. Thus, the eigenvalues become simpler, including a zero eigenvalue and a non-zero eigenvalue. Based on the non-zero eigenvalue, the relation between the gain margin and the PLL parameters is established, and an optimizing design method of the PLL parameters is proposed to achieve system stability and satisfactory PLL dynamic response. Finally, experimental results from a 10-kVA prototype of three-phase grid-connected inverter are provided to verify the validity of the proposed design method.
A second-order generalized integrator (SOGI) is a resonant regulator with a pair of complex-conjugate poles, and therefore, with infinite magnitude at its center frequency. Thanks to this property, ...one can put together a set of <inline-formula><tex-math notation="LaTeX">m</tex-math></inline-formula> SOGIs in an elegant way and decompose a single-phase signal into its constituent frequency components and detect their amplitude and phase angle. Such a configuration, which is often referred to as the multi-SOGI (MSOGI) structure, requires a frequency estimator to adapt the center frequency of SOGIs to frequency changes. This frequency estimation is often provided by interconnecting the MSOGI structure with a basic frequency-locked loop (FLL) or phase-locked loop (PLL). The resulting structures are known as the MSOGI-FLL and MSOGI-PLL. These structures and their close variants are mathematically difficult to analyze probably because of the lack of a linear model for these systems. This article aims to bridge this research gap. First, it is shown how linear time-periodic (LTP) models of the MSOGI-FLL and MSOGI-PLL can be obtained. The model verification, obtaining open-loop harmonic transfer function from the LTP model, and LTP stability assessment of MSOGI-based synchronization systems are the next parts of this article. Finally, some close variants of the MSOGI-FLL/PLL are considered and their modeling and stability assessment are briefly discussed.
