This article demonstrates how to simultaneously utilize three degrees of modulation freedom, e.g. switching state selection (SSS), zero-sequence signal injection (ZSI) and redundant level modulation ...(RLM) to enable the voltage balancing in certain multilevel topologies, such as the presented five-level (5L), hybrid-clamped (HC) converter topologies, 5L-HC-E and 5L-HC-2E, as reference examples. Phase opposition disposition (POD), is another degree of modulation freedom used for the common-mode voltage (CMV) mitigation. The proposed control scheme is developed for the two most challenging 5L-HC device-reduced high-voltage topologies, which cannot be balanced with traditional modulation freedoms because voltage balance of one capacitor would worsen the balance of other capacitors. Only full utilization of degrees of modulation freedom with higher control ability can solve the balancing problem. A comprehensive explanation of these four control degrees of freedom is presented in this article. Power loss analysis is also provided with high modulation index and power factor. The proposed closed-loop control method can be easily implemented in a digital controller without requiring any mandatory proportional-integral (PI) controllers, since it only relies on closed-form analytical models and basic logic operators. The effectiveness of the control method has been verified in simulation and experiments covering the range of full modulation indexes (0-1.15), full power factors (0-1), various fundamental frequencies (5-50Hz), unequal load and capacitor degradation.
In voltage source inverters (VSI), the output voltage is synthesized in an average sense using pulsewidth modulation (PWM) techniques. In space vector PWM techniques, the average realization of the ...space vector using volt-sec balance results in an instantaneous error that influences the dc bus current. The instantaneous ac load error voltage maps onto the dc bus derive the dc bus current ripple signatures that would be useful to size the dc capacitor. Exploiting concept of instantaneous mapping of ac error voltage onto the dc bus through power factor axis coordinates, in this work, the unprecedented dc ripple voltage computational method is presented. The established synchronous power factor reference frame ensures accurate mapping of ac error voltage onto the dc bus and makes the computational method independent of sensing actual ac load current unlike conventional methods. With the eliminated actual load current dependence, the proposed model can predict the minimum dc voltage ripple yield switching sequence for VSIs at different loading conditions. The efficacy of the proposed model in terms of optimum switching sequence elicitation is demonstrated on the dual inverter configuration experimentally considering the inflated switching stress due to two inverter's switching.
In the motor systems driven by sinusoidal pulse width modulation (SPWM) three-phase inverters, the peaks of common-mode (CM) voltage are so high that it will cause many negative effects. In this ...paper, a hybrid filter is presented to reduce the CM voltage (CMV) and the differential-mode (DM) harmonics in a three-phase inverter with carrier peak position modulation (CPPM). Because the use of CPPM strategy in the inverter can ensure that the output CMV will be only two levels in any condition, the simple active CM filter (composed of a half-bridge circuit) in the hybrid filter can effectively suppress the output CMV and CM current. The passive filter in the hybrid filter consists of an added single tuned filter and the original DM low-pass filter. The single tuned filter is designed to lower the DM harmonics, which are aggravated by the CPPM strategy in the carrier frequency band. Through the experiments, the validity of CMV and DM harmonics suppression by the hybrid filter in the three-phase inverter is verified and the calculation-control active CM filter is proved to be the best in the optional schemes.
Leakage current minimization is one of the most important considerations in transformerless photovoltaic (PV) inverters. In the past, various transformerless PV inverter topologies have been ...introduced, with leakage current minimized by the means of galvanic isolation and common-mode voltage (CMV) clamping. The galvanic isolation can be achieved via dc-decoupling or ac-decoupling, for isolation on the dc- or ac-side of the inverter, respectively. It has been shown that the latter provides lower losses due to the reduced switch count in conduction path. Nevertheless, leakage current cannot be simply eliminated by galvanic isolation and modulation techniques, due to the presence of switches' junction capacitances and resonant circuit effects. Hence, CMV clamping is used in some topologies to completely eliminate the leakage current. In this paper, several recently proposed transformerless PV inverters with different galvanic isolation methods and CMV clamping technique are analyzed and compared. A simple modified H-bridge zero-voltage state rectifier is also proposed, to combine the benefits of the low-loss ac-decoupling method and the complete leakage current elimination of the CMV clamping method. The performances of different topologies, in terms of CMV, leakage current, total harmonic distortion, losses and efficiencies are compared. The analyses are done theoretically and via simulation studies, and further validated with experimental results. This paper is helpful for the researchers to choose the appropriate topology for transformerless PV applications and to provide the design principles in terms of common-mode behavior and efficiency.
This article describes an integrated voltage-boosting technique, which is essential to achieve compatibility between low-voltage photovoltaic (PV) panels and high-voltage dc links needed for dc-to-ac ...conversion. To achieve the twin objectives of voltage-boosting and multilevel inversion, this article proposes a transformerless T-type nine-level hybrid boost inverter. To improve the efficiency in the boosting stage of the proposed converter system, a significant portion of the PV energy is directly transferred from the PV source to the load, while the other part is processed through an interleaved converter, which is fused with the inverter. Thus, the proposed converter ensures a higher power density and reduces the power ratings of the semiconductor devices. This article also introduces a modified zone-based pulsewidth modulation (PWM) technique, which achieves a complete elimination of the switching frequency voltage transitions in the total common-mode voltage (TCMV). Thus, this technique mitigates the generation of leakage current while preserving the advantages of conventional multilevel inverters such as low <inline-formula> <tex-math notation="LaTeX">\text{d}v/\text{d}t </tex-math></inline-formula> and inductive power capability. Besides that, a rigorous mathematical analysis for the common-mode equivalent circuit of the proposed configuration is also presented in this article. Detailed simulation and experimental studies are carried out to validate the feasibility of the proposed configuration.
Nowadays, neutral point voltage (NPV) balancing control and leakage current (LC) reduction methods are considered to improve the reliability of transformerless three-level T-type (3LT 2 ) inverter. ...Medium vector pulse width modulation (MVPWM) method can control the inverter operation to eliminate the LC; however, is powerless to balance the NPV. Alternatively, discontinuous PWM (DPWM) methods can be implemented to balance the NPV. In this article, a hybrid method for transformerless 3LT 2 inverter is proposed to simultaneously minimize the LC and accomplish balancing control in case of NPV unbalancing. The proposed method applies MVPWM switching patterns to eliminate LC while the NPV is balanced. If the NPV becomes unbalanced, it applies specific switching patterns of the DPWM methods as alternative patterns to balance the NPV with minimal LC. Accordingly, the proposed method not only maintains the LC elimination advantage of the MVPWM method but also realizes the NPV balancing capability without any topology modification or adding electrical components. Noteworthy, even the NPV balancing is accomplished with minimal flow of the LC. The proposed method is carrier-based PWM, which shortens execution time and simplifies practical implementation. Experimental tests have been accomplished and results demonstrate the effectiveness of the proposed method on adding the NPV balancing capability with minimal LC to the MVPWM method.
This paper presents an improved dc-link voltage balancing algorithm for a three-level neutral-point-clamped inverter by considering phase current direction. Detailed studies on the effects of change ...in load current direction on the dc-link capacitor voltages are presented. A maximum value of power factor is numerically derived, above which it affects the capacitor voltage balancing capability. Compared with the previously presented research work, the inputs to the space-vector pulsewidth-modulation block are the three phase currents and the difference between the two capacitor voltages. Depending on the states of the two dc-link capacitor voltages and phase current direction, redundant voltage vector sequences are selected. The selected vectors keep the capacitor voltage deviations within 5% of the total dc-link voltage. Two zero switching vectors (i.e., PPP and NNN) are also removed from all subsectors of the earlier proposed strategy, which one used to produce higher common-mode voltages. Detailed simulation and experimental results are presented in this paper for a 6.0-kW surface permanent-magnet synchronous machine. Both the simulation and experimental results show the required performance of the proposed system.
This article presents a two-stage T-type hybrid five-level transformerless inverter (TLI) for grid-connected photovoltaic (PV) applications. The proposed T-type hybrid five-level inverter and its ...level-shifted pulsewidth modulation scheme offers reduced leakage current by eliminating the high-frequency variations and sudden transitions in the voltage across PV parasitic capacitance C PV and a path for the negative current in all the modes of operation under unity and nonunity power factor conditions of the grid without degrading the waveform quality. Moreover, in this article, the proposed inverter is integrated with a traditional three-level boost converter (3LBC) for boosting the lower PV voltage to higher dc-link voltage and also to extract maximum power from the PV source. The 3LBC provides high efficiency and reduced input inductor size for the same power rating over the conventional boost converter. The simulation results of the proposed system are presented using MATLAB software, and a 500-W experimental prototype is constructed and tested in the laboratory to validate the feasibility of the proposed configuration. Finally, a comparison of the proposed inverter with other five-level TLI topologies is presented to highlight its merits.
In this paper, a Filter-Clamped (FC) inverter is employed as a three-phase grid-connected Transformerless Photovoltaic (TLPV) inverter. TLPV inverters are more efficient and more cost-effective ...compared to the alternatives based on high and low-frequency isolation transformers. On the other hand, TLPV inverters generate high leakage current due to the removal of the isolation transformer. Prior-art TLPV topologies have been developed to overcome this issue by either adding more semiconductor switches to block potential leakage current paths or modifying the control method. In contrast, the FC inverter addresses the leakage current issue without adding any extra component or improving the control technique. Thus, it is a promising solution to TLPV systems. Having decreased the leakage current, the FC inverter improves the THD of grid injected current and the efficiency compared to the conventional three-phase Full-Bridge (FB) inverter. Simulations and experiments are provided to validate the effectiveness of the FC inverter in terms of reduced leakage current, improved grid current THD, and improved overall efficiency.
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